32 #if CL_TARGET_OPENCL_VERSION <= 110
33 #define CL_DEVICE_DOUBLE_FP_CONFIG 0x1032
37 #define CL_DEVICE_HALF_FP_CONFIG 0x1033
56 #define cl_APPLE_SetMemObjectDestructor 1
57 cl_int CL_API_ENTRY clSetMemObjectDestructorAPPLE( cl_mem memobj,
58 void (* pfn_notify)(cl_mem memobj,
void * user_data),
59 void * user_data) CL_API_SUFFIX__VERSION_1_0;
70 #define cl_APPLE_ContextLoggingFunctions 1
71 extern void CL_API_ENTRY clLogMessagesToSystemLogAPPLE(
const char * errstr,
72 const void * private_info,
74 void * user_data) CL_API_SUFFIX__VERSION_1_0;
77 extern void CL_API_ENTRY clLogMessagesToStdoutAPPLE(
const char * errstr,
78 const void * private_info,
80 void * user_data) CL_API_SUFFIX__VERSION_1_0;
83 extern void CL_API_ENTRY clLogMessagesToStderrAPPLE(
const char * errstr,
84 const void * private_info,
86 void * user_data) CL_API_SUFFIX__VERSION_1_0;
95 #define CL_PLATFORM_ICD_SUFFIX_KHR 0x0920
98 #define CL_PLATFORM_NOT_FOUND_KHR -1001
100 extern CL_API_ENTRY cl_int CL_API_CALL
101 clIcdGetPlatformIDsKHR(cl_uint num_entries,
102 cl_platform_id * platforms,
103 cl_uint * num_platforms);
105 typedef CL_API_ENTRY cl_int
106 (CL_API_CALL *clIcdGetPlatformIDsKHR_fn)(cl_uint num_entries,
107 cl_platform_id * platforms,
108 cl_uint * num_platforms);
114 #define cl_khr_il_program 1
119 #define CL_DEVICE_IL_VERSION_KHR 0x105B
124 #define CL_PROGRAM_IL_KHR 0x1169
126 extern CL_API_ENTRY cl_program CL_API_CALL
127 clCreateProgramWithILKHR(cl_context context,
130 cl_int * errcode_ret);
132 typedef CL_API_ENTRY cl_program
133 (CL_API_CALL *clCreateProgramWithILKHR_fn)(cl_context context,
136 cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_2;
157 #define CL_DEVICE_IMAGE_PITCH_ALIGNMENT_KHR 0x104A
158 #define CL_DEVICE_IMAGE_BASE_ADDRESS_ALIGNMENT_KHR 0x104B
165 #define CL_CONTEXT_MEMORY_INITIALIZE_KHR 0x2030
172 #define CL_CONTEXT_TERMINATED_KHR -1121
174 #define CL_DEVICE_TERMINATE_CAPABILITY_KHR 0x2031
175 #define CL_CONTEXT_TERMINATE_KHR 0x2032
177 #define cl_khr_terminate_context 1
178 extern CL_API_ENTRY cl_int CL_API_CALL
179 clTerminateContextKHR(cl_context context) CL_API_SUFFIX__VERSION_1_2;
181 typedef CL_API_ENTRY cl_int
182 (CL_API_CALL *clTerminateContextKHR_fn)(cl_context context) CL_API_SUFFIX__VERSION_1_2;
192 #define CL_DEVICE_SPIR_VERSIONS 0x40E0
193 #define CL_PROGRAM_BINARY_TYPE_INTERMEDIATE 0x40E1
199 #define cl_khr_create_command_queue 1
201 typedef cl_properties cl_queue_properties_khr;
203 extern CL_API_ENTRY cl_command_queue CL_API_CALL
204 clCreateCommandQueueWithPropertiesKHR(cl_context context,
206 const cl_queue_properties_khr* properties,
207 cl_int* errcode_ret) CL_API_SUFFIX__VERSION_1_2;
209 typedef CL_API_ENTRY cl_command_queue
210 (CL_API_CALL *clCreateCommandQueueWithPropertiesKHR_fn)(cl_context context,
212 const cl_queue_properties_khr* properties,
213 cl_int* errcode_ret) CL_API_SUFFIX__VERSION_1_2;
221 #define CL_DEVICE_COMPUTE_CAPABILITY_MAJOR_NV 0x4000
222 #define CL_DEVICE_COMPUTE_CAPABILITY_MINOR_NV 0x4001
223 #define CL_DEVICE_REGISTERS_PER_BLOCK_NV 0x4002
224 #define CL_DEVICE_WARP_SIZE_NV 0x4003
225 #define CL_DEVICE_GPU_OVERLAP_NV 0x4004
226 #define CL_DEVICE_KERNEL_EXEC_TIMEOUT_NV 0x4005
227 #define CL_DEVICE_INTEGRATED_MEMORY_NV 0x4006
234 #define CL_DEVICE_PROFILING_TIMER_OFFSET_AMD 0x4036
235 #define CL_DEVICE_TOPOLOGY_AMD 0x4037
236 #define CL_DEVICE_BOARD_NAME_AMD 0x4038
237 #define CL_DEVICE_GLOBAL_FREE_MEMORY_AMD 0x4039
238 #define CL_DEVICE_SIMD_PER_COMPUTE_UNIT_AMD 0x4040
239 #define CL_DEVICE_SIMD_WIDTH_AMD 0x4041
240 #define CL_DEVICE_SIMD_INSTRUCTION_WIDTH_AMD 0x4042
241 #define CL_DEVICE_WAVEFRONT_WIDTH_AMD 0x4043
242 #define CL_DEVICE_GLOBAL_MEM_CHANNELS_AMD 0x4044
243 #define CL_DEVICE_GLOBAL_MEM_CHANNEL_BANKS_AMD 0x4045
244 #define CL_DEVICE_GLOBAL_MEM_CHANNEL_BANK_WIDTH_AMD 0x4046
245 #define CL_DEVICE_LOCAL_MEM_SIZE_PER_COMPUTE_UNIT_AMD 0x4047
246 #define CL_DEVICE_LOCAL_MEM_BANKS_AMD 0x4048
247 #define CL_DEVICE_THREAD_TRACE_SUPPORTED_AMD 0x4049
248 #define CL_DEVICE_GFXIP_MAJOR_AMD 0x404A
249 #define CL_DEVICE_GFXIP_MINOR_AMD 0x404B
250 #define CL_DEVICE_AVAILABLE_ASYNC_QUEUES_AMD 0x404C
251 #define CL_DEVICE_PREFERRED_WORK_GROUP_SIZE_AMD 0x4030
252 #define CL_DEVICE_MAX_WORK_GROUP_SIZE_AMD 0x4031
253 #define CL_DEVICE_PREFERRED_CONSTANT_BUFFER_SIZE_AMD 0x4033
254 #define CL_DEVICE_PCIE_ID_AMD 0x4034
261 #define CL_PRINTF_CALLBACK_ARM 0x40B0
262 #define CL_PRINTF_BUFFERSIZE_ARM 0x40B1
268 #define cl_ext_device_fission 1
270 extern CL_API_ENTRY cl_int CL_API_CALL
271 clReleaseDeviceEXT(cl_device_id device) CL_API_SUFFIX__VERSION_1_1;
273 typedef CL_API_ENTRY cl_int
274 (CL_API_CALL *clReleaseDeviceEXT_fn)(cl_device_id device) CL_API_SUFFIX__VERSION_1_1;
276 extern CL_API_ENTRY cl_int CL_API_CALL
277 clRetainDeviceEXT(cl_device_id device) CL_API_SUFFIX__VERSION_1_1;
279 typedef CL_API_ENTRY cl_int
280 (CL_API_CALL *clRetainDeviceEXT_fn)(cl_device_id device) CL_API_SUFFIX__VERSION_1_1;
282 typedef cl_ulong cl_device_partition_property_ext;
283 extern CL_API_ENTRY cl_int CL_API_CALL
284 clCreateSubDevicesEXT(cl_device_id in_device,
285 const cl_device_partition_property_ext * properties,
287 cl_device_id * out_devices,
288 cl_uint * num_devices) CL_API_SUFFIX__VERSION_1_1;
290 typedef CL_API_ENTRY cl_int
291 (CL_API_CALL * clCreateSubDevicesEXT_fn)(cl_device_id in_device,
292 const cl_device_partition_property_ext * properties,
294 cl_device_id * out_devices,
295 cl_uint * num_devices) CL_API_SUFFIX__VERSION_1_1;
298 #define CL_DEVICE_PARTITION_EQUALLY_EXT 0x4050
299 #define CL_DEVICE_PARTITION_BY_COUNTS_EXT 0x4051
300 #define CL_DEVICE_PARTITION_BY_NAMES_EXT 0x4052
301 #define CL_DEVICE_PARTITION_BY_AFFINITY_DOMAIN_EXT 0x4053
304 #define CL_DEVICE_PARENT_DEVICE_EXT 0x4054
305 #define CL_DEVICE_PARTITION_TYPES_EXT 0x4055
306 #define CL_DEVICE_AFFINITY_DOMAINS_EXT 0x4056
307 #define CL_DEVICE_REFERENCE_COUNT_EXT 0x4057
308 #define CL_DEVICE_PARTITION_STYLE_EXT 0x4058
311 #define CL_DEVICE_PARTITION_FAILED_EXT -1057
312 #define CL_INVALID_PARTITION_COUNT_EXT -1058
313 #define CL_INVALID_PARTITION_NAME_EXT -1059
316 #define CL_AFFINITY_DOMAIN_L1_CACHE_EXT 0x1
317 #define CL_AFFINITY_DOMAIN_L2_CACHE_EXT 0x2
318 #define CL_AFFINITY_DOMAIN_L3_CACHE_EXT 0x3
319 #define CL_AFFINITY_DOMAIN_L4_CACHE_EXT 0x4
320 #define CL_AFFINITY_DOMAIN_NUMA_EXT 0x10
321 #define CL_AFFINITY_DOMAIN_NEXT_FISSIONABLE_EXT 0x100
324 #define CL_PROPERTIES_LIST_END_EXT ((cl_device_partition_property_ext) 0)
325 #define CL_PARTITION_BY_COUNTS_LIST_END_EXT ((cl_device_partition_property_ext) 0)
326 #define CL_PARTITION_BY_NAMES_LIST_END_EXT ((cl_device_partition_property_ext) 0 - 1)
332 #define cl_ext_migrate_memobject 1
334 typedef cl_bitfield cl_mem_migration_flags_ext;
336 #define CL_MIGRATE_MEM_OBJECT_HOST_EXT 0x1
338 #define CL_COMMAND_MIGRATE_MEM_OBJECT_EXT 0x4040
340 extern CL_API_ENTRY cl_int CL_API_CALL
341 clEnqueueMigrateMemObjectEXT(cl_command_queue command_queue,
342 cl_uint num_mem_objects,
343 const cl_mem * mem_objects,
344 cl_mem_migration_flags_ext flags,
345 cl_uint num_events_in_wait_list,
346 const cl_event * event_wait_list,
349 typedef CL_API_ENTRY cl_int
350 (CL_API_CALL *clEnqueueMigrateMemObjectEXT_fn)(cl_command_queue command_queue,
351 cl_uint num_mem_objects,
352 const cl_mem * mem_objects,
353 cl_mem_migration_flags_ext flags,
354 cl_uint num_events_in_wait_list,
355 const cl_event * event_wait_list,
362 #define cl_ext_cxx_for_opencl 1
364 #define CL_DEVICE_CXX_FOR_OPENCL_NUMERIC_VERSION_EXT 0x4230
369 #define cl_qcom_ext_host_ptr 1
371 #define CL_MEM_EXT_HOST_PTR_QCOM (1 << 29)
373 #define CL_DEVICE_EXT_MEM_PADDING_IN_BYTES_QCOM 0x40A0
374 #define CL_DEVICE_PAGE_SIZE_QCOM 0x40A1
375 #define CL_IMAGE_ROW_ALIGNMENT_QCOM 0x40A2
376 #define CL_IMAGE_SLICE_ALIGNMENT_QCOM 0x40A3
377 #define CL_MEM_HOST_UNCACHED_QCOM 0x40A4
378 #define CL_MEM_HOST_WRITEBACK_QCOM 0x40A5
379 #define CL_MEM_HOST_WRITETHROUGH_QCOM 0x40A6
380 #define CL_MEM_HOST_WRITE_COMBINING_QCOM 0x40A7
382 typedef cl_uint cl_image_pitch_info_qcom;
384 extern CL_API_ENTRY cl_int CL_API_CALL
385 clGetDeviceImageInfoQCOM(cl_device_id device,
389 cl_image_pitch_info_qcom param_name,
390 size_t param_value_size,
392 size_t *param_value_size_ret);
398 cl_uint allocation_type;
401 cl_uint host_cache_policy;
411 #define CL_MEM_HOST_IOCOHERENT_QCOM 0x40A9
418 #define CL_MEM_ION_HOST_PTR_QCOM 0x40A8
439 #define CL_MEM_ANDROID_NATIVE_BUFFER_HOST_PTR_QCOM 0x40C6
458 #define CL_NV21_IMG 0x40D0
459 #define CL_YV12_IMG 0x40D1
467 #define CL_MEM_USE_UNCACHED_CPU_MEMORY_IMG (1 << 26)
468 #define CL_MEM_USE_CACHED_CPU_MEMORY_IMG (1 << 27)
474 #define cl_img_use_gralloc_ptr 1
477 #define CL_MEM_USE_GRALLOC_PTR_IMG (1 << 28)
480 #define CL_COMMAND_ACQUIRE_GRALLOC_OBJECTS_IMG 0x40D2
481 #define CL_COMMAND_RELEASE_GRALLOC_OBJECTS_IMG 0x40D3
484 #define CL_GRALLOC_RESOURCE_NOT_ACQUIRED_IMG 0x40D4
485 #define CL_INVALID_GRALLOC_OBJECT_IMG 0x40D5
487 extern CL_API_ENTRY cl_int CL_API_CALL
488 clEnqueueAcquireGrallocObjectsIMG(cl_command_queue command_queue,
490 const cl_mem * mem_objects,
491 cl_uint num_events_in_wait_list,
492 const cl_event * event_wait_list,
493 cl_event * event) CL_API_SUFFIX__VERSION_1_2;
495 extern CL_API_ENTRY cl_int CL_API_CALL
496 clEnqueueReleaseGrallocObjectsIMG(cl_command_queue command_queue,
498 const cl_mem * mem_objects,
499 cl_uint num_events_in_wait_list,
500 const cl_event * event_wait_list,
501 cl_event * event) CL_API_SUFFIX__VERSION_1_2;
506 #define cl_img_generate_mipmap 1
508 typedef cl_uint cl_mipmap_filter_mode_img;
511 #define CL_MIPMAP_FILTER_ANY_IMG 0x0
512 #define CL_MIPMAP_FILTER_BOX_IMG 0x1
515 #define CL_COMMAND_GENERATE_MIPMAP_IMG 0x40D6
517 extern CL_API_ENTRY cl_int CL_API_CALL
518 clEnqueueGenerateMipmapIMG(cl_command_queue command_queue,
521 cl_mipmap_filter_mode_img mipmap_filter_mode,
522 const size_t *array_region,
523 const size_t *mip_region,
524 cl_uint num_events_in_wait_list,
525 const cl_event *event_wait_list,
526 cl_event *event) CL_API_SUFFIX__VERSION_1_2;
531 #define cl_img_mem_properties 1
534 #define CL_MEM_ALLOC_FLAGS_IMG 0x40D7
537 typedef cl_bitfield cl_mem_alloc_flags_img;
540 #define CL_MEM_ALLOC_RELAX_REQUIREMENTS_IMG (1 << 0)
545 #define cl_khr_subgroups 1
547 #if !defined(CL_VERSION_2_1)
552 typedef cl_uint cl_kernel_sub_group_info;
556 #define CL_KERNEL_MAX_SUB_GROUP_SIZE_FOR_NDRANGE_KHR 0x2033
557 #define CL_KERNEL_SUB_GROUP_COUNT_FOR_NDRANGE_KHR 0x2034
559 extern CL_API_ENTRY cl_int CL_API_CALL
560 clGetKernelSubGroupInfoKHR(cl_kernel in_kernel,
561 cl_device_id in_device,
562 cl_kernel_sub_group_info param_name,
563 size_t input_value_size,
564 const void * input_value,
565 size_t param_value_size,
567 size_t * param_value_size_ret) CL_API_SUFFIX__VERSION_2_0_DEPRECATED;
569 typedef CL_API_ENTRY cl_int
570 (CL_API_CALL * clGetKernelSubGroupInfoKHR_fn)(cl_kernel in_kernel,
571 cl_device_id in_device,
572 cl_kernel_sub_group_info param_name,
573 size_t input_value_size,
574 const void * input_value,
575 size_t param_value_size,
577 size_t * param_value_size_ret) CL_API_SUFFIX__VERSION_2_0_DEPRECATED;
585 #define CL_SAMPLER_MIP_FILTER_MODE_KHR 0x1155
586 #define CL_SAMPLER_LOD_MIN_KHR 0x1156
587 #define CL_SAMPLER_LOD_MAX_KHR 0x1157
595 #define cl_khr_priority_hints 1
597 typedef cl_uint cl_queue_priority_khr;
600 #define CL_QUEUE_PRIORITY_KHR 0x1096
603 #define CL_QUEUE_PRIORITY_HIGH_KHR (1<<0)
604 #define CL_QUEUE_PRIORITY_MED_KHR (1<<1)
605 #define CL_QUEUE_PRIORITY_LOW_KHR (1<<2)
613 #define cl_khr_throttle_hints 1
615 typedef cl_uint cl_queue_throttle_khr;
618 #define CL_QUEUE_THROTTLE_KHR 0x1097
621 #define CL_QUEUE_THROTTLE_HIGH_KHR (1<<0)
622 #define CL_QUEUE_THROTTLE_MED_KHR (1<<1)
623 #define CL_QUEUE_THROTTLE_LOW_KHR (1<<2)
631 #define cl_khr_subgroup_named_barrier 1
634 #define CL_DEVICE_MAX_NAMED_BARRIER_COUNT_KHR 0x2035
641 #define cl_khr_extended_versioning 1
643 #define CL_VERSION_MAJOR_BITS_KHR (10)
644 #define CL_VERSION_MINOR_BITS_KHR (10)
645 #define CL_VERSION_PATCH_BITS_KHR (12)
647 #define CL_VERSION_MAJOR_MASK_KHR ((1 << CL_VERSION_MAJOR_BITS_KHR) - 1)
648 #define CL_VERSION_MINOR_MASK_KHR ((1 << CL_VERSION_MINOR_BITS_KHR) - 1)
649 #define CL_VERSION_PATCH_MASK_KHR ((1 << CL_VERSION_PATCH_BITS_KHR) - 1)
651 #define CL_VERSION_MAJOR_KHR(version) ((version) >> (CL_VERSION_MINOR_BITS_KHR + CL_VERSION_PATCH_BITS_KHR))
652 #define CL_VERSION_MINOR_KHR(version) (((version) >> CL_VERSION_PATCH_BITS_KHR) & CL_VERSION_MINOR_MASK_KHR)
653 #define CL_VERSION_PATCH_KHR(version) ((version) & CL_VERSION_PATCH_MASK_KHR)
655 #define CL_MAKE_VERSION_KHR(major, minor, patch) \
656 ((((major) & CL_VERSION_MAJOR_MASK_KHR) << (CL_VERSION_MINOR_BITS_KHR + CL_VERSION_PATCH_BITS_KHR)) | \
657 (((minor) & CL_VERSION_MINOR_MASK_KHR) << CL_VERSION_PATCH_BITS_KHR) | \
658 ((patch) & CL_VERSION_PATCH_MASK_KHR))
660 typedef cl_uint cl_version_khr;
662 #define CL_NAME_VERSION_MAX_NAME_SIZE_KHR 64
666 cl_version_khr version;
667 char name[CL_NAME_VERSION_MAX_NAME_SIZE_KHR];
671 #define CL_PLATFORM_NUMERIC_VERSION_KHR 0x0906
672 #define CL_PLATFORM_EXTENSIONS_WITH_VERSION_KHR 0x0907
675 #define CL_DEVICE_NUMERIC_VERSION_KHR 0x105E
676 #define CL_DEVICE_OPENCL_C_NUMERIC_VERSION_KHR 0x105F
677 #define CL_DEVICE_EXTENSIONS_WITH_VERSION_KHR 0x1060
678 #define CL_DEVICE_ILS_WITH_VERSION_KHR 0x1061
679 #define CL_DEVICE_BUILT_IN_KERNELS_WITH_VERSION_KHR 0x1062
685 #define cl_khr_device_uuid 1
687 #define CL_UUID_SIZE_KHR 16
688 #define CL_LUID_SIZE_KHR 8
690 #define CL_DEVICE_UUID_KHR 0x106A
691 #define CL_DRIVER_UUID_KHR 0x106B
692 #define CL_DEVICE_LUID_VALID_KHR 0x106C
693 #define CL_DEVICE_LUID_KHR 0x106D
694 #define CL_DEVICE_NODE_MASK_KHR 0x106E
700 #define cl_arm_import_memory 1
702 typedef intptr_t cl_import_properties_arm;
705 #define CL_IMPORT_TYPE_ARM 0x40B2
708 #define CL_IMPORT_TYPE_HOST_ARM 0x40B3
711 #define CL_IMPORT_TYPE_DMA_BUF_ARM 0x40B4
714 #define CL_IMPORT_TYPE_PROTECTED_ARM 0x40B5
717 #define CL_IMPORT_TYPE_ANDROID_HARDWARE_BUFFER_ARM 0x41E2
720 #define CL_IMPORT_DMA_BUF_DATA_CONSISTENCY_WITH_HOST_ARM 0x41E3
723 #define CL_IMPORT_ANDROID_HARDWARE_BUFFER_PLANE_INDEX_ARM 0x41EF
726 #define CL_IMPORT_ANDROID_HARDWARE_BUFFER_LAYER_INDEX_ARM 0x41F0
729 #define CL_IMPORT_MEMORY_WHOLE_ALLOCATION_ARM SIZE_MAX
747 extern CL_API_ENTRY cl_mem CL_API_CALL
748 clImportMemoryARM( cl_context context,
750 const cl_import_properties_arm *properties,
753 cl_int *errcode_ret) CL_API_SUFFIX__VERSION_1_0;
759 #define cl_arm_shared_virtual_memory 1
762 #define CL_DEVICE_SVM_CAPABILITIES_ARM 0x40B6
765 #define CL_MEM_USES_SVM_POINTER_ARM 0x40B7
768 #define CL_KERNEL_EXEC_INFO_SVM_PTRS_ARM 0x40B8
769 #define CL_KERNEL_EXEC_INFO_SVM_FINE_GRAIN_SYSTEM_ARM 0x40B9
772 #define CL_COMMAND_SVM_FREE_ARM 0x40BA
773 #define CL_COMMAND_SVM_MEMCPY_ARM 0x40BB
774 #define CL_COMMAND_SVM_MEMFILL_ARM 0x40BC
775 #define CL_COMMAND_SVM_MAP_ARM 0x40BD
776 #define CL_COMMAND_SVM_UNMAP_ARM 0x40BE
779 #define CL_DEVICE_SVM_COARSE_GRAIN_BUFFER_ARM (1 << 0)
780 #define CL_DEVICE_SVM_FINE_GRAIN_BUFFER_ARM (1 << 1)
781 #define CL_DEVICE_SVM_FINE_GRAIN_SYSTEM_ARM (1 << 2)
782 #define CL_DEVICE_SVM_ATOMICS_ARM (1 << 3)
785 #define CL_MEM_SVM_FINE_GRAIN_BUFFER_ARM (1 << 10)
786 #define CL_MEM_SVM_ATOMICS_ARM (1 << 11)
788 typedef cl_bitfield cl_svm_mem_flags_arm;
789 typedef cl_uint cl_kernel_exec_info_arm;
790 typedef cl_bitfield cl_device_svm_capabilities_arm;
792 extern CL_API_ENTRY
void * CL_API_CALL
793 clSVMAllocARM(cl_context context,
794 cl_svm_mem_flags_arm flags,
796 cl_uint alignment) CL_API_SUFFIX__VERSION_1_2;
798 extern CL_API_ENTRY
void CL_API_CALL
799 clSVMFreeARM(cl_context context,
800 void * svm_pointer) CL_API_SUFFIX__VERSION_1_2;
802 extern CL_API_ENTRY cl_int CL_API_CALL
803 clEnqueueSVMFreeARM(cl_command_queue command_queue,
804 cl_uint num_svm_pointers,
805 void * svm_pointers[],
806 void (CL_CALLBACK * pfn_free_func)(cl_command_queue queue,
807 cl_uint num_svm_pointers,
808 void * svm_pointers[],
811 cl_uint num_events_in_wait_list,
812 const cl_event * event_wait_list,
813 cl_event * event) CL_API_SUFFIX__VERSION_1_2;
815 extern CL_API_ENTRY cl_int CL_API_CALL
816 clEnqueueSVMMemcpyARM(cl_command_queue command_queue,
817 cl_bool blocking_copy,
819 const void * src_ptr,
821 cl_uint num_events_in_wait_list,
822 const cl_event * event_wait_list,
823 cl_event * event) CL_API_SUFFIX__VERSION_1_2;
825 extern CL_API_ENTRY cl_int CL_API_CALL
826 clEnqueueSVMMemFillARM(cl_command_queue command_queue,
828 const void * pattern,
831 cl_uint num_events_in_wait_list,
832 const cl_event * event_wait_list,
833 cl_event * event) CL_API_SUFFIX__VERSION_1_2;
835 extern CL_API_ENTRY cl_int CL_API_CALL
836 clEnqueueSVMMapARM(cl_command_queue command_queue,
837 cl_bool blocking_map,
841 cl_uint num_events_in_wait_list,
842 const cl_event * event_wait_list,
843 cl_event * event) CL_API_SUFFIX__VERSION_1_2;
845 extern CL_API_ENTRY cl_int CL_API_CALL
846 clEnqueueSVMUnmapARM(cl_command_queue command_queue,
848 cl_uint num_events_in_wait_list,
849 const cl_event * event_wait_list,
850 cl_event * event) CL_API_SUFFIX__VERSION_1_2;
852 extern CL_API_ENTRY cl_int CL_API_CALL
853 clSetKernelArgSVMPointerARM(cl_kernel kernel,
855 const void * arg_value) CL_API_SUFFIX__VERSION_1_2;
857 extern CL_API_ENTRY cl_int CL_API_CALL
858 clSetKernelExecInfoARM(cl_kernel kernel,
859 cl_kernel_exec_info_arm param_name,
860 size_t param_value_size,
861 const void * param_value) CL_API_SUFFIX__VERSION_1_2;
867 #ifdef CL_VERSION_1_2
869 #define cl_arm_get_core_id 1
872 #define CL_DEVICE_COMPUTE_UNITS_BITFIELD_ARM 0x40BF
880 #define cl_arm_job_slot_selection 1
883 #define CL_DEVICE_JOB_SLOTS_ARM 0x41E0
886 #define CL_QUEUE_JOB_SLOT_ARM 0x41E1
892 #define cl_arm_scheduling_controls 1
894 typedef cl_bitfield cl_device_scheduling_controls_capabilities_arm;
897 #define CL_DEVICE_SCHEDULING_CONTROLS_CAPABILITIES_ARM 0x41E4
899 #define CL_DEVICE_SCHEDULING_KERNEL_BATCHING_ARM (1 << 0)
900 #define CL_DEVICE_SCHEDULING_WORKGROUP_BATCH_SIZE_ARM (1 << 1)
901 #define CL_DEVICE_SCHEDULING_WORKGROUP_BATCH_SIZE_MODIFIER_ARM (1 << 2)
902 #define CL_DEVICE_SCHEDULING_DEFERRED_FLUSH_ARM (1 << 3)
903 #define CL_DEVICE_SCHEDULING_REGISTER_ALLOCATION_ARM (1 << 4)
905 #define CL_DEVICE_SUPPORTED_REGISTER_ALLOCATIONS_ARM 0x41EB
908 #define CL_KERNEL_EXEC_INFO_WORKGROUP_BATCH_SIZE_ARM 0x41E5
909 #define CL_KERNEL_EXEC_INFO_WORKGROUP_BATCH_SIZE_MODIFIER_ARM 0x41E6
912 #define CL_QUEUE_KERNEL_BATCHING_ARM 0x41E7
913 #define CL_QUEUE_DEFERRED_FLUSH_ARM 0x41EC
919 #define cl_arm_controlled_kernel_termination 1
922 #define CL_COMMAND_TERMINATED_ITSELF_WITH_FAILURE_ARM -1108
925 #define CL_DEVICE_CONTROLLED_TERMINATION_CAPABILITIES_ARM 0x41EE
928 typedef cl_bitfield cl_device_controlled_termination_capabilities_arm;
930 #define CL_DEVICE_CONTROLLED_TERMINATION_SUCCESS_ARM (1 << 0)
931 #define CL_DEVICE_CONTROLLED_TERMINATION_FAILURE_ARM (1 << 1)
932 #define CL_DEVICE_CONTROLLED_TERMINATION_QUERY_ARM (1 << 2)
935 #define CL_EVENT_COMMAND_TERMINATION_REASON_ARM 0x41ED
938 typedef cl_uint cl_command_termination_reason_arm;
940 #define CL_COMMAND_TERMINATION_COMPLETION_ARM 0
941 #define CL_COMMAND_TERMINATION_CONTROLLED_SUCCESS_ARM 1
942 #define CL_COMMAND_TERMINATION_CONTROLLED_FAILURE_ARM 2
943 #define CL_COMMAND_TERMINATION_ERROR_ARM 3
949 #define cl_intel_thread_local_exec 1
951 #define CL_QUEUE_THREAD_LOCAL_EXEC_ENABLE_INTEL (((cl_bitfield)1) << 31)
957 #define cl_intel_device_partition_by_names 1
959 #define CL_DEVICE_PARTITION_BY_NAMES_INTEL 0x4052
960 #define CL_PARTITION_BY_NAMES_LIST_END_INTEL -1
968 #define cl_intel_accelerator 1
969 #define cl_intel_motion_estimation 1
970 #define cl_intel_advanced_motion_estimation 1
972 typedef struct _cl_accelerator_intel* cl_accelerator_intel;
973 typedef cl_uint cl_accelerator_type_intel;
974 typedef cl_uint cl_accelerator_info_intel;
977 cl_uint mb_block_type;
978 cl_uint subpixel_mode;
979 cl_uint sad_adjust_mode;
980 cl_uint search_path_type;
984 #define CL_INVALID_ACCELERATOR_INTEL -1094
985 #define CL_INVALID_ACCELERATOR_TYPE_INTEL -1095
986 #define CL_INVALID_ACCELERATOR_DESCRIPTOR_INTEL -1096
987 #define CL_ACCELERATOR_TYPE_NOT_SUPPORTED_INTEL -1097
990 #define CL_ACCELERATOR_TYPE_MOTION_ESTIMATION_INTEL 0x0
993 #define CL_ACCELERATOR_DESCRIPTOR_INTEL 0x4090
994 #define CL_ACCELERATOR_REFERENCE_COUNT_INTEL 0x4091
995 #define CL_ACCELERATOR_CONTEXT_INTEL 0x4092
996 #define CL_ACCELERATOR_TYPE_INTEL 0x4093
999 #define CL_ME_MB_TYPE_16x16_INTEL 0x0
1000 #define CL_ME_MB_TYPE_8x8_INTEL 0x1
1001 #define CL_ME_MB_TYPE_4x4_INTEL 0x2
1003 #define CL_ME_SUBPIXEL_MODE_INTEGER_INTEL 0x0
1004 #define CL_ME_SUBPIXEL_MODE_HPEL_INTEL 0x1
1005 #define CL_ME_SUBPIXEL_MODE_QPEL_INTEL 0x2
1007 #define CL_ME_SAD_ADJUST_MODE_NONE_INTEL 0x0
1008 #define CL_ME_SAD_ADJUST_MODE_HAAR_INTEL 0x1
1010 #define CL_ME_SEARCH_PATH_RADIUS_2_2_INTEL 0x0
1011 #define CL_ME_SEARCH_PATH_RADIUS_4_4_INTEL 0x1
1012 #define CL_ME_SEARCH_PATH_RADIUS_16_12_INTEL 0x5
1014 #define CL_ME_SKIP_BLOCK_TYPE_16x16_INTEL 0x0
1015 #define CL_ME_CHROMA_INTRA_PREDICT_ENABLED_INTEL 0x1
1016 #define CL_ME_LUMA_INTRA_PREDICT_ENABLED_INTEL 0x2
1017 #define CL_ME_SKIP_BLOCK_TYPE_8x8_INTEL 0x4
1019 #define CL_ME_FORWARD_INPUT_MODE_INTEL 0x1
1020 #define CL_ME_BACKWARD_INPUT_MODE_INTEL 0x2
1021 #define CL_ME_BIDIRECTION_INPUT_MODE_INTEL 0x3
1023 #define CL_ME_BIDIR_WEIGHT_QUARTER_INTEL 16
1024 #define CL_ME_BIDIR_WEIGHT_THIRD_INTEL 21
1025 #define CL_ME_BIDIR_WEIGHT_HALF_INTEL 32
1026 #define CL_ME_BIDIR_WEIGHT_TWO_THIRD_INTEL 43
1027 #define CL_ME_BIDIR_WEIGHT_THREE_QUARTER_INTEL 48
1029 #define CL_ME_COST_PENALTY_NONE_INTEL 0x0
1030 #define CL_ME_COST_PENALTY_LOW_INTEL 0x1
1031 #define CL_ME_COST_PENALTY_NORMAL_INTEL 0x2
1032 #define CL_ME_COST_PENALTY_HIGH_INTEL 0x3
1034 #define CL_ME_COST_PRECISION_QPEL_INTEL 0x0
1035 #define CL_ME_COST_PRECISION_HPEL_INTEL 0x1
1036 #define CL_ME_COST_PRECISION_PEL_INTEL 0x2
1037 #define CL_ME_COST_PRECISION_DPEL_INTEL 0x3
1039 #define CL_ME_LUMA_PREDICTOR_MODE_VERTICAL_INTEL 0x0
1040 #define CL_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_INTEL 0x1
1041 #define CL_ME_LUMA_PREDICTOR_MODE_DC_INTEL 0x2
1042 #define CL_ME_LUMA_PREDICTOR_MODE_DIAGONAL_DOWN_LEFT_INTEL 0x3
1044 #define CL_ME_LUMA_PREDICTOR_MODE_DIAGONAL_DOWN_RIGHT_INTEL 0x4
1045 #define CL_ME_LUMA_PREDICTOR_MODE_PLANE_INTEL 0x4
1046 #define CL_ME_LUMA_PREDICTOR_MODE_VERTICAL_RIGHT_INTEL 0x5
1047 #define CL_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_DOWN_INTEL 0x6
1048 #define CL_ME_LUMA_PREDICTOR_MODE_VERTICAL_LEFT_INTEL 0x7
1049 #define CL_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_UP_INTEL 0x8
1051 #define CL_ME_CHROMA_PREDICTOR_MODE_DC_INTEL 0x0
1052 #define CL_ME_CHROMA_PREDICTOR_MODE_HORIZONTAL_INTEL 0x1
1053 #define CL_ME_CHROMA_PREDICTOR_MODE_VERTICAL_INTEL 0x2
1054 #define CL_ME_CHROMA_PREDICTOR_MODE_PLANE_INTEL 0x3
1057 #define CL_DEVICE_ME_VERSION_INTEL 0x407E
1059 #define CL_ME_VERSION_LEGACY_INTEL 0x0
1060 #define CL_ME_VERSION_ADVANCED_VER_1_INTEL 0x1
1061 #define CL_ME_VERSION_ADVANCED_VER_2_INTEL 0x2
1063 extern CL_API_ENTRY cl_accelerator_intel CL_API_CALL
1064 clCreateAcceleratorINTEL(
1066 cl_accelerator_type_intel accelerator_type,
1067 size_t descriptor_size,
1068 const void* descriptor,
1069 cl_int* errcode_ret) CL_API_SUFFIX__VERSION_1_2;
1071 typedef CL_API_ENTRY cl_accelerator_intel (CL_API_CALL *clCreateAcceleratorINTEL_fn)(
1073 cl_accelerator_type_intel accelerator_type,
1074 size_t descriptor_size,
1075 const void* descriptor,
1076 cl_int* errcode_ret) CL_API_SUFFIX__VERSION_1_2;
1078 extern CL_API_ENTRY cl_int CL_API_CALL
1079 clGetAcceleratorInfoINTEL(
1080 cl_accelerator_intel accelerator,
1081 cl_accelerator_info_intel param_name,
1082 size_t param_value_size,
1084 size_t* param_value_size_ret) CL_API_SUFFIX__VERSION_1_2;
1086 typedef CL_API_ENTRY cl_int (CL_API_CALL *clGetAcceleratorInfoINTEL_fn)(
1087 cl_accelerator_intel accelerator,
1088 cl_accelerator_info_intel param_name,
1089 size_t param_value_size,
1091 size_t* param_value_size_ret) CL_API_SUFFIX__VERSION_1_2;
1093 extern CL_API_ENTRY cl_int CL_API_CALL
1094 clRetainAcceleratorINTEL(
1095 cl_accelerator_intel accelerator) CL_API_SUFFIX__VERSION_1_2;
1097 typedef CL_API_ENTRY cl_int (CL_API_CALL *clRetainAcceleratorINTEL_fn)(
1098 cl_accelerator_intel accelerator) CL_API_SUFFIX__VERSION_1_2;
1100 extern CL_API_ENTRY cl_int CL_API_CALL
1101 clReleaseAcceleratorINTEL(
1102 cl_accelerator_intel accelerator) CL_API_SUFFIX__VERSION_1_2;
1104 typedef CL_API_ENTRY cl_int (CL_API_CALL *clReleaseAcceleratorINTEL_fn)(
1105 cl_accelerator_intel accelerator) CL_API_SUFFIX__VERSION_1_2;
1111 #define cl_intel_simultaneous_sharing 1
1113 #define CL_DEVICE_SIMULTANEOUS_INTEROPS_INTEL 0x4104
1114 #define CL_DEVICE_NUM_SIMULTANEOUS_INTEROPS_INTEL 0x4105
1120 #define cl_intel_egl_image_yuv 1
1122 #define CL_EGL_YUV_PLANE_INTEL 0x4107
1128 #define cl_intel_packed_yuv 1
1130 #define CL_YUYV_INTEL 0x4076
1131 #define CL_UYVY_INTEL 0x4077
1132 #define CL_YVYU_INTEL 0x4078
1133 #define CL_VYUY_INTEL 0x4079
1139 #define cl_intel_required_subgroup_size 1
1141 #define CL_DEVICE_SUB_GROUP_SIZES_INTEL 0x4108
1142 #define CL_KERNEL_SPILL_MEM_SIZE_INTEL 0x4109
1143 #define CL_KERNEL_COMPILE_SUB_GROUP_SIZE_INTEL 0x410A
1149 #define cl_intel_driver_diagnostics 1
1151 typedef cl_uint cl_diagnostics_verbose_level;
1153 #define CL_CONTEXT_SHOW_DIAGNOSTICS_INTEL 0x4106
1155 #define CL_CONTEXT_DIAGNOSTICS_LEVEL_ALL_INTEL ( 0xff )
1156 #define CL_CONTEXT_DIAGNOSTICS_LEVEL_GOOD_INTEL ( 1 )
1157 #define CL_CONTEXT_DIAGNOSTICS_LEVEL_BAD_INTEL ( 1 << 1 )
1158 #define CL_CONTEXT_DIAGNOSTICS_LEVEL_NEUTRAL_INTEL ( 1 << 2 )
1164 #define CL_NV12_INTEL 0x410E
1166 #define CL_MEM_NO_ACCESS_INTEL ( 1 << 24 )
1167 #define CL_MEM_ACCESS_FLAGS_UNRESTRICTED_INTEL ( 1 << 25 )
1169 #define CL_DEVICE_PLANAR_YUV_MAX_WIDTH_INTEL 0x417E
1170 #define CL_DEVICE_PLANAR_YUV_MAX_HEIGHT_INTEL 0x417F
1176 #define CL_DEVICE_AVC_ME_VERSION_INTEL 0x410B
1177 #define CL_DEVICE_AVC_ME_SUPPORTS_TEXTURE_SAMPLER_USE_INTEL 0x410C
1178 #define CL_DEVICE_AVC_ME_SUPPORTS_PREEMPTION_INTEL 0x410D
1180 #define CL_AVC_ME_VERSION_0_INTEL 0x0
1181 #define CL_AVC_ME_VERSION_1_INTEL 0x1
1183 #define CL_AVC_ME_MAJOR_16x16_INTEL 0x0
1184 #define CL_AVC_ME_MAJOR_16x8_INTEL 0x1
1185 #define CL_AVC_ME_MAJOR_8x16_INTEL 0x2
1186 #define CL_AVC_ME_MAJOR_8x8_INTEL 0x3
1188 #define CL_AVC_ME_MINOR_8x8_INTEL 0x0
1189 #define CL_AVC_ME_MINOR_8x4_INTEL 0x1
1190 #define CL_AVC_ME_MINOR_4x8_INTEL 0x2
1191 #define CL_AVC_ME_MINOR_4x4_INTEL 0x3
1193 #define CL_AVC_ME_MAJOR_FORWARD_INTEL 0x0
1194 #define CL_AVC_ME_MAJOR_BACKWARD_INTEL 0x1
1195 #define CL_AVC_ME_MAJOR_BIDIRECTIONAL_INTEL 0x2
1197 #define CL_AVC_ME_PARTITION_MASK_ALL_INTEL 0x0
1198 #define CL_AVC_ME_PARTITION_MASK_16x16_INTEL 0x7E
1199 #define CL_AVC_ME_PARTITION_MASK_16x8_INTEL 0x7D
1200 #define CL_AVC_ME_PARTITION_MASK_8x16_INTEL 0x7B
1201 #define CL_AVC_ME_PARTITION_MASK_8x8_INTEL 0x77
1202 #define CL_AVC_ME_PARTITION_MASK_8x4_INTEL 0x6F
1203 #define CL_AVC_ME_PARTITION_MASK_4x8_INTEL 0x5F
1204 #define CL_AVC_ME_PARTITION_MASK_4x4_INTEL 0x3F
1206 #define CL_AVC_ME_SEARCH_WINDOW_EXHAUSTIVE_INTEL 0x0
1207 #define CL_AVC_ME_SEARCH_WINDOW_SMALL_INTEL 0x1
1208 #define CL_AVC_ME_SEARCH_WINDOW_TINY_INTEL 0x2
1209 #define CL_AVC_ME_SEARCH_WINDOW_EXTRA_TINY_INTEL 0x3
1210 #define CL_AVC_ME_SEARCH_WINDOW_DIAMOND_INTEL 0x4
1211 #define CL_AVC_ME_SEARCH_WINDOW_LARGE_DIAMOND_INTEL 0x5
1212 #define CL_AVC_ME_SEARCH_WINDOW_RESERVED0_INTEL 0x6
1213 #define CL_AVC_ME_SEARCH_WINDOW_RESERVED1_INTEL 0x7
1214 #define CL_AVC_ME_SEARCH_WINDOW_CUSTOM_INTEL 0x8
1215 #define CL_AVC_ME_SEARCH_WINDOW_16x12_RADIUS_INTEL 0x9
1216 #define CL_AVC_ME_SEARCH_WINDOW_4x4_RADIUS_INTEL 0x2
1217 #define CL_AVC_ME_SEARCH_WINDOW_2x2_RADIUS_INTEL 0xa
1219 #define CL_AVC_ME_SAD_ADJUST_MODE_NONE_INTEL 0x0
1220 #define CL_AVC_ME_SAD_ADJUST_MODE_HAAR_INTEL 0x2
1222 #define CL_AVC_ME_SUBPIXEL_MODE_INTEGER_INTEL 0x0
1223 #define CL_AVC_ME_SUBPIXEL_MODE_HPEL_INTEL 0x1
1224 #define CL_AVC_ME_SUBPIXEL_MODE_QPEL_INTEL 0x3
1226 #define CL_AVC_ME_COST_PRECISION_QPEL_INTEL 0x0
1227 #define CL_AVC_ME_COST_PRECISION_HPEL_INTEL 0x1
1228 #define CL_AVC_ME_COST_PRECISION_PEL_INTEL 0x2
1229 #define CL_AVC_ME_COST_PRECISION_DPEL_INTEL 0x3
1231 #define CL_AVC_ME_BIDIR_WEIGHT_QUARTER_INTEL 0x10
1232 #define CL_AVC_ME_BIDIR_WEIGHT_THIRD_INTEL 0x15
1233 #define CL_AVC_ME_BIDIR_WEIGHT_HALF_INTEL 0x20
1234 #define CL_AVC_ME_BIDIR_WEIGHT_TWO_THIRD_INTEL 0x2B
1235 #define CL_AVC_ME_BIDIR_WEIGHT_THREE_QUARTER_INTEL 0x30
1237 #define CL_AVC_ME_BORDER_REACHED_LEFT_INTEL 0x0
1238 #define CL_AVC_ME_BORDER_REACHED_RIGHT_INTEL 0x2
1239 #define CL_AVC_ME_BORDER_REACHED_TOP_INTEL 0x4
1240 #define CL_AVC_ME_BORDER_REACHED_BOTTOM_INTEL 0x8
1242 #define CL_AVC_ME_SKIP_BLOCK_PARTITION_16x16_INTEL 0x0
1243 #define CL_AVC_ME_SKIP_BLOCK_PARTITION_8x8_INTEL 0x4000
1245 #define CL_AVC_ME_SKIP_BLOCK_16x16_FORWARD_ENABLE_INTEL ( 0x1 << 24 )
1246 #define CL_AVC_ME_SKIP_BLOCK_16x16_BACKWARD_ENABLE_INTEL ( 0x2 << 24 )
1247 #define CL_AVC_ME_SKIP_BLOCK_16x16_DUAL_ENABLE_INTEL ( 0x3 << 24 )
1248 #define CL_AVC_ME_SKIP_BLOCK_8x8_FORWARD_ENABLE_INTEL ( 0x55 << 24 )
1249 #define CL_AVC_ME_SKIP_BLOCK_8x8_BACKWARD_ENABLE_INTEL ( 0xAA << 24 )
1250 #define CL_AVC_ME_SKIP_BLOCK_8x8_DUAL_ENABLE_INTEL ( 0xFF << 24 )
1251 #define CL_AVC_ME_SKIP_BLOCK_8x8_0_FORWARD_ENABLE_INTEL ( 0x1 << 24 )
1252 #define CL_AVC_ME_SKIP_BLOCK_8x8_0_BACKWARD_ENABLE_INTEL ( 0x2 << 24 )
1253 #define CL_AVC_ME_SKIP_BLOCK_8x8_1_FORWARD_ENABLE_INTEL ( 0x1 << 26 )
1254 #define CL_AVC_ME_SKIP_BLOCK_8x8_1_BACKWARD_ENABLE_INTEL ( 0x2 << 26 )
1255 #define CL_AVC_ME_SKIP_BLOCK_8x8_2_FORWARD_ENABLE_INTEL ( 0x1 << 28 )
1256 #define CL_AVC_ME_SKIP_BLOCK_8x8_2_BACKWARD_ENABLE_INTEL ( 0x2 << 28 )
1257 #define CL_AVC_ME_SKIP_BLOCK_8x8_3_FORWARD_ENABLE_INTEL ( 0x1 << 30 )
1258 #define CL_AVC_ME_SKIP_BLOCK_8x8_3_BACKWARD_ENABLE_INTEL ( 0x2 << 30 )
1260 #define CL_AVC_ME_BLOCK_BASED_SKIP_4x4_INTEL 0x00
1261 #define CL_AVC_ME_BLOCK_BASED_SKIP_8x8_INTEL 0x80
1263 #define CL_AVC_ME_INTRA_16x16_INTEL 0x0
1264 #define CL_AVC_ME_INTRA_8x8_INTEL 0x1
1265 #define CL_AVC_ME_INTRA_4x4_INTEL 0x2
1267 #define CL_AVC_ME_INTRA_LUMA_PARTITION_MASK_16x16_INTEL 0x6
1268 #define CL_AVC_ME_INTRA_LUMA_PARTITION_MASK_8x8_INTEL 0x5
1269 #define CL_AVC_ME_INTRA_LUMA_PARTITION_MASK_4x4_INTEL 0x3
1271 #define CL_AVC_ME_INTRA_NEIGHBOR_LEFT_MASK_ENABLE_INTEL 0x60
1272 #define CL_AVC_ME_INTRA_NEIGHBOR_UPPER_MASK_ENABLE_INTEL 0x10
1273 #define CL_AVC_ME_INTRA_NEIGHBOR_UPPER_RIGHT_MASK_ENABLE_INTEL 0x8
1274 #define CL_AVC_ME_INTRA_NEIGHBOR_UPPER_LEFT_MASK_ENABLE_INTEL 0x4
1276 #define CL_AVC_ME_LUMA_PREDICTOR_MODE_VERTICAL_INTEL 0x0
1277 #define CL_AVC_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_INTEL 0x1
1278 #define CL_AVC_ME_LUMA_PREDICTOR_MODE_DC_INTEL 0x2
1279 #define CL_AVC_ME_LUMA_PREDICTOR_MODE_DIAGONAL_DOWN_LEFT_INTEL 0x3
1280 #define CL_AVC_ME_LUMA_PREDICTOR_MODE_DIAGONAL_DOWN_RIGHT_INTEL 0x4
1281 #define CL_AVC_ME_LUMA_PREDICTOR_MODE_PLANE_INTEL 0x4
1282 #define CL_AVC_ME_LUMA_PREDICTOR_MODE_VERTICAL_RIGHT_INTEL 0x5
1283 #define CL_AVC_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_DOWN_INTEL 0x6
1284 #define CL_AVC_ME_LUMA_PREDICTOR_MODE_VERTICAL_LEFT_INTEL 0x7
1285 #define CL_AVC_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_UP_INTEL 0x8
1286 #define CL_AVC_ME_CHROMA_PREDICTOR_MODE_DC_INTEL 0x0
1287 #define CL_AVC_ME_CHROMA_PREDICTOR_MODE_HORIZONTAL_INTEL 0x1
1288 #define CL_AVC_ME_CHROMA_PREDICTOR_MODE_VERTICAL_INTEL 0x2
1289 #define CL_AVC_ME_CHROMA_PREDICTOR_MODE_PLANE_INTEL 0x3
1291 #define CL_AVC_ME_FRAME_FORWARD_INTEL 0x1
1292 #define CL_AVC_ME_FRAME_BACKWARD_INTEL 0x2
1293 #define CL_AVC_ME_FRAME_DUAL_INTEL 0x3
1295 #define CL_AVC_ME_SLICE_TYPE_PRED_INTEL 0x0
1296 #define CL_AVC_ME_SLICE_TYPE_BPRED_INTEL 0x1
1297 #define CL_AVC_ME_SLICE_TYPE_INTRA_INTEL 0x2
1299 #define CL_AVC_ME_INTERLACED_SCAN_TOP_FIELD_INTEL 0x0
1300 #define CL_AVC_ME_INTERLACED_SCAN_BOTTOM_FIELD_INTEL 0x1
1308 #define cl_intel_unified_shared_memory 1
1311 #define CL_DEVICE_HOST_MEM_CAPABILITIES_INTEL 0x4190
1312 #define CL_DEVICE_DEVICE_MEM_CAPABILITIES_INTEL 0x4191
1313 #define CL_DEVICE_SINGLE_DEVICE_SHARED_MEM_CAPABILITIES_INTEL 0x4192
1314 #define CL_DEVICE_CROSS_DEVICE_SHARED_MEM_CAPABILITIES_INTEL 0x4193
1315 #define CL_DEVICE_SHARED_SYSTEM_MEM_CAPABILITIES_INTEL 0x4194
1317 typedef cl_bitfield cl_device_unified_shared_memory_capabilities_intel;
1320 #define CL_UNIFIED_SHARED_MEMORY_ACCESS_INTEL (1 << 0)
1321 #define CL_UNIFIED_SHARED_MEMORY_ATOMIC_ACCESS_INTEL (1 << 1)
1322 #define CL_UNIFIED_SHARED_MEMORY_CONCURRENT_ACCESS_INTEL (1 << 2)
1323 #define CL_UNIFIED_SHARED_MEMORY_CONCURRENT_ATOMIC_ACCESS_INTEL (1 << 3)
1325 typedef cl_properties cl_mem_properties_intel;
1328 #define CL_MEM_ALLOC_FLAGS_INTEL 0x4195
1330 typedef cl_bitfield cl_mem_alloc_flags_intel;
1333 #define CL_MEM_ALLOC_WRITE_COMBINED_INTEL (1 << 0)
1335 typedef cl_uint cl_mem_info_intel;
1338 #define CL_MEM_ALLOC_TYPE_INTEL 0x419A
1339 #define CL_MEM_ALLOC_BASE_PTR_INTEL 0x419B
1340 #define CL_MEM_ALLOC_SIZE_INTEL 0x419C
1341 #define CL_MEM_ALLOC_DEVICE_INTEL 0x419D
1344 typedef cl_uint cl_unified_shared_memory_type_intel;
1347 #define CL_MEM_TYPE_UNKNOWN_INTEL 0x4196
1348 #define CL_MEM_TYPE_HOST_INTEL 0x4197
1349 #define CL_MEM_TYPE_DEVICE_INTEL 0x4198
1350 #define CL_MEM_TYPE_SHARED_INTEL 0x4199
1352 typedef cl_uint cl_mem_advice_intel;
1358 #define CL_KERNEL_EXEC_INFO_INDIRECT_HOST_ACCESS_INTEL 0x4200
1359 #define CL_KERNEL_EXEC_INFO_INDIRECT_DEVICE_ACCESS_INTEL 0x4201
1360 #define CL_KERNEL_EXEC_INFO_INDIRECT_SHARED_ACCESS_INTEL 0x4202
1361 #define CL_KERNEL_EXEC_INFO_USM_PTRS_INTEL 0x4203
1364 #define CL_COMMAND_MEMFILL_INTEL 0x4204
1365 #define CL_COMMAND_MEMCPY_INTEL 0x4205
1366 #define CL_COMMAND_MIGRATEMEM_INTEL 0x4206
1367 #define CL_COMMAND_MEMADVISE_INTEL 0x4207
1369 extern CL_API_ENTRY
void* CL_API_CALL
1370 clHostMemAllocINTEL(
1372 const cl_mem_properties_intel* properties,
1375 cl_int* errcode_ret);
1377 typedef CL_API_ENTRY
void* (CL_API_CALL *
1378 clHostMemAllocINTEL_fn)(
1380 const cl_mem_properties_intel* properties,
1383 cl_int* errcode_ret);
1385 extern CL_API_ENTRY
void* CL_API_CALL
1386 clDeviceMemAllocINTEL(
1388 cl_device_id device,
1389 const cl_mem_properties_intel* properties,
1392 cl_int* errcode_ret);
1394 typedef CL_API_ENTRY
void* (CL_API_CALL *
1395 clDeviceMemAllocINTEL_fn)(
1397 cl_device_id device,
1398 const cl_mem_properties_intel* properties,
1401 cl_int* errcode_ret);
1403 extern CL_API_ENTRY
void* CL_API_CALL
1404 clSharedMemAllocINTEL(
1406 cl_device_id device,
1407 const cl_mem_properties_intel* properties,
1410 cl_int* errcode_ret);
1412 typedef CL_API_ENTRY
void* (CL_API_CALL *
1413 clSharedMemAllocINTEL_fn)(
1415 cl_device_id device,
1416 const cl_mem_properties_intel* properties,
1419 cl_int* errcode_ret);
1421 extern CL_API_ENTRY cl_int CL_API_CALL
1426 typedef CL_API_ENTRY cl_int (CL_API_CALL *
1431 extern CL_API_ENTRY cl_int CL_API_CALL
1432 clMemBlockingFreeINTEL(
1436 typedef CL_API_ENTRY cl_int (CL_API_CALL *
1437 clMemBlockingFreeINTEL_fn)(
1441 extern CL_API_ENTRY cl_int CL_API_CALL
1442 clGetMemAllocInfoINTEL(
1445 cl_mem_info_intel param_name,
1446 size_t param_value_size,
1448 size_t* param_value_size_ret);
1450 typedef CL_API_ENTRY cl_int (CL_API_CALL *
1451 clGetMemAllocInfoINTEL_fn)(
1454 cl_mem_info_intel param_name,
1455 size_t param_value_size,
1457 size_t* param_value_size_ret);
1459 extern CL_API_ENTRY cl_int CL_API_CALL
1460 clSetKernelArgMemPointerINTEL(
1463 const void* arg_value);
1465 typedef CL_API_ENTRY cl_int (CL_API_CALL *
1466 clSetKernelArgMemPointerINTEL_fn)(
1469 const void* arg_value);
1471 extern CL_API_ENTRY cl_int CL_API_CALL
1472 clEnqueueMemsetINTEL(
1473 cl_command_queue command_queue,
1477 cl_uint num_events_in_wait_list,
1478 const cl_event* event_wait_list,
1481 typedef CL_API_ENTRY cl_int (CL_API_CALL *
1482 clEnqueueMemsetINTEL_fn)(
1483 cl_command_queue command_queue,
1487 cl_uint num_events_in_wait_list,
1488 const cl_event* event_wait_list,
1491 extern CL_API_ENTRY cl_int CL_API_CALL
1492 clEnqueueMemFillINTEL(
1493 cl_command_queue command_queue,
1495 const void* pattern,
1496 size_t pattern_size,
1498 cl_uint num_events_in_wait_list,
1499 const cl_event* event_wait_list,
1502 typedef CL_API_ENTRY cl_int (CL_API_CALL *
1503 clEnqueueMemFillINTEL_fn)(
1504 cl_command_queue command_queue,
1506 const void* pattern,
1507 size_t pattern_size,
1509 cl_uint num_events_in_wait_list,
1510 const cl_event* event_wait_list,
1513 extern CL_API_ENTRY cl_int CL_API_CALL
1514 clEnqueueMemcpyINTEL(
1515 cl_command_queue command_queue,
1518 const void* src_ptr,
1520 cl_uint num_events_in_wait_list,
1521 const cl_event* event_wait_list,
1524 typedef CL_API_ENTRY cl_int (CL_API_CALL *
1525 clEnqueueMemcpyINTEL_fn)(
1526 cl_command_queue command_queue,
1529 const void* src_ptr,
1531 cl_uint num_events_in_wait_list,
1532 const cl_event* event_wait_list,
1535 #ifdef CL_VERSION_1_2
1540 extern CL_API_ENTRY cl_int CL_API_CALL
1541 clEnqueueMigrateMemINTEL(
1542 cl_command_queue command_queue,
1545 cl_mem_migration_flags flags,
1546 cl_uint num_events_in_wait_list,
1547 const cl_event* event_wait_list,
1550 typedef CL_API_ENTRY cl_int (CL_API_CALL *
1551 clEnqueueMigrateMemINTEL_fn)(
1552 cl_command_queue command_queue,
1555 cl_mem_migration_flags flags,
1556 cl_uint num_events_in_wait_list,
1557 const cl_event* event_wait_list,
1562 extern CL_API_ENTRY cl_int CL_API_CALL
1563 clEnqueueMemAdviseINTEL(
1564 cl_command_queue command_queue,
1567 cl_mem_advice_intel advice,
1568 cl_uint num_events_in_wait_list,
1569 const cl_event* event_wait_list,
1572 typedef CL_API_ENTRY cl_int (CL_API_CALL *
1573 clEnqueueMemAdviseINTEL_fn)(
1574 cl_command_queue command_queue,
1577 cl_mem_advice_intel advice,
1578 cl_uint num_events_in_wait_list,
1579 const cl_event* event_wait_list,
1586 #define cl_intel_create_buffer_with_properties 1
1588 extern CL_API_ENTRY cl_mem CL_API_CALL
1589 clCreateBufferWithPropertiesINTEL(
1591 const cl_mem_properties_intel* properties,
1595 cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_0;
1597 typedef CL_API_ENTRY cl_mem (CL_API_CALL *
1598 clCreateBufferWithPropertiesINTEL_fn)(
1600 const cl_mem_properties_intel* properties,
1604 cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_0;
1610 #define CL_MEM_CHANNEL_INTEL 0x4213
1616 #define cl_intel_mem_force_host_memory 1
1619 #define CL_MEM_FORCE_HOST_MEMORY_INTEL (1 << 20)
1624 #define cl_intel_command_queue_families 1
1626 typedef cl_bitfield cl_command_queue_capabilities_intel;
1628 #define CL_QUEUE_FAMILY_MAX_NAME_SIZE_INTEL 64
1631 cl_command_queue_properties properties;
1632 cl_command_queue_capabilities_intel capabilities;
1634 char name[CL_QUEUE_FAMILY_MAX_NAME_SIZE_INTEL];
1638 #define CL_DEVICE_QUEUE_FAMILY_PROPERTIES_INTEL 0x418B
1641 #define CL_QUEUE_FAMILY_INTEL 0x418C
1642 #define CL_QUEUE_INDEX_INTEL 0x418D
1645 #define CL_QUEUE_DEFAULT_CAPABILITIES_INTEL 0
1646 #define CL_QUEUE_CAPABILITY_CREATE_SINGLE_QUEUE_EVENTS_INTEL (1 << 0)
1647 #define CL_QUEUE_CAPABILITY_CREATE_CROSS_QUEUE_EVENTS_INTEL (1 << 1)
1648 #define CL_QUEUE_CAPABILITY_SINGLE_QUEUE_EVENT_WAIT_LIST_INTEL (1 << 2)
1649 #define CL_QUEUE_CAPABILITY_CROSS_QUEUE_EVENT_WAIT_LIST_INTEL (1 << 3)
1650 #define CL_QUEUE_CAPABILITY_TRANSFER_BUFFER_INTEL (1 << 8)
1651 #define CL_QUEUE_CAPABILITY_TRANSFER_BUFFER_RECT_INTEL (1 << 9)
1652 #define CL_QUEUE_CAPABILITY_MAP_BUFFER_INTEL (1 << 10)
1653 #define CL_QUEUE_CAPABILITY_FILL_BUFFER_INTEL (1 << 11)
1654 #define CL_QUEUE_CAPABILITY_TRANSFER_IMAGE_INTEL (1 << 12)
1655 #define CL_QUEUE_CAPABILITY_MAP_IMAGE_INTEL (1 << 13)
1656 #define CL_QUEUE_CAPABILITY_FILL_IMAGE_INTEL (1 << 14)
1657 #define CL_QUEUE_CAPABILITY_TRANSFER_BUFFER_IMAGE_INTEL (1 << 15)
1658 #define CL_QUEUE_CAPABILITY_TRANSFER_IMAGE_BUFFER_INTEL (1 << 16)
1659 #define CL_QUEUE_CAPABILITY_MARKER_INTEL (1 << 24)
1660 #define CL_QUEUE_CAPABILITY_BARRIER_INTEL (1 << 25)
1661 #define CL_QUEUE_CAPABILITY_KERNEL_INTEL (1 << 26)