u8m(mL$mediatek,mt8173-evbmediatek,mt8173 +!7MediaTek MT8173 evaluation boardaliases=/soc/ovl@1400c000B/soc/ovl@1400d000G/soc/rdma@1400e000M/soc/rdma@1400f000S/soc/rdma@14010000Y/soc/wdma@14011000_/soc/wdma@14012000e/soc/color@14013000l/soc/color@14014000s/soc/split@14018000z/soc/split@14019000/soc/dpi@1401d000/soc/dsi@1401b000/soc/dsi@1401c000/soc/rdma@14001000/soc/rdma@14002000/soc/rsz@14003000/soc/rsz@14004000/soc/rsz@14005000/soc/wdma@14006000/soc/wrot@14007000/soc/wrot@14008000/soc/serial@11002000/soc/serial@11003000/soc/serial@11004000/soc/serial@11005000cpus+cpu-mapcluster0core0core1cluster1core0core1cpu@0cpuarm,cortex-a53 psci/>cpu@1cpuarm,cortex-a53 psci>cpu@100cpuarm,cortex-a57 psci/>cpu@101cpuarm,cortex-a57 psci>idle-statesFpscicpu-sleep-0arm,idle-stateSdu@>psci#arm,psci-1.0arm,psci-0.2arm,pscismcoscillator0 fixed-clockclk26m> oscillator1 fixed-clock}clk32koscillator2 fixed-clockcpum_ckthermal-zonescpu_thermal,tripstrip-point0> Jpassivetrip-point1>LJpassive>cpu_crit0>8J criticalcooling-mapsmap0U Zi map1U Zireserved-memory+vvpu_dma_mem_region@b7000000shared-dma-pool P}>timerarm,armv8-timer 0   soc+ simple-busvclock-controller@10000000mediatek,mt8173-topckgen > power-controller@10001000 mediatek,mt8173-infracfgsyscon > power-controller@10003000mediatek,mt8173-pericfgsyscon 0>syscfg_pctl_a@10005000%mediatek,mt8173-pctl-a-syscfgsyscon P> pinctrl@0x1000b000mediatek,mt8173-pinctrl  $>xxx>;pins1#i2c0>pins1-.2i2c1>pins1}~2i2c2>pins1+,2i2c3>pins1jk2i2c4> pins12i2c6>!pins1de2disp_pwm0_pins>9pins1W?mmc0default>"pins_cmd_dat$9:;<=>?@BJpins_clkA#pins_rstDJmmc1default>&pins_cmd_datIJKLNWJfpins_clkM#Wpins_insertJmmc0>#pins_cmd_dat$9:;<=>?@BWJepins_clkAW#epins_rstDJmmc1>'pins_cmd_datIJKLNWJfpins_clkMW#fusb_iddig_pull_up>0pins_iddigJusb_iddig_pull_down>1pins_iddig#spi0>pins_spiEFGHscpsys@10006000mediatek,mt8173-scpsysf `z U X imfgmmvencvenc_lt >watchdog@10007000(mediatek,mt8173-wdtmediatek,mt6589-wdt ptimer@10008000,mediatek,mt8173-timermediatek,mt6577-timer  z xpwrap@1000d000mediatek,mt8173-pwrap pwrap  pwrapz  spiwrapmt6397mediatek,mt6397  mt6397regulatormediatek,mt6397-regulatorbuck_vpca15 buck_vpca15vpca15 `p0*buck_vpca7 buck_vpca7vpca7 `p0>sbuck_vsramca15buck_vsramca15 vsramca15 `p0*buck_vsramca7buck_vsramca7 vsramca7 `p0*buck_vcore buck_vcorevcore `p0*buck_vgpu buck_vgpuvgpu `p0>sbuck_vdrm buck_vdrmvdrmO\0*buck_vio18 buck_vio18vio18 6`0*>%ldo_vtcxo ldo_vtcxovtcxo*ldo_va28 ldo_va28va28*ldo_vcama ldo_vcamavcama`*>ldo_vio28 ldo_vio28vio28*ldo_vusb ldo_vusbvusb>-ldo_vmcldo_vmcvmcw@2Z>>)ldo_vmch ldo_vmchvmch-2Z>>(ldo_vemc3v3 ldo_vemc3v3 vemc_3v3-2Z>>$ldo_vgp1 ldo_vgp1vcamd2Z>ldo_vgp2 ldo_vgp2vcamioB@2Z>ldo_vgp3 ldo_vgp3vcamafO2Z>ldo_vgp4 ldo_vgp4vgp4O2Z>ldo_vgp5 ldo_vgp5vgp5O->ldo_vgp6 ldo_vgp6vgp6O2Z>ldo_vibr ldo_vibrvibr 2Z>cec@10013000mediatek,mt8173-cec 0 z Zokayvpu@10020000mediatek,mt8173-vpu   tcmcfg_reg z gmaina>5intpol-controller@10200620.mediatek,mt8173-sysirqmediatek,mt6577-sysirq    >iommu@10205000mediatek,mt8173-m4u  P z bclko~>4efuse@10206000mediatek,mt8173-efuse  `+calib@528 ( >clock-controller@10209000mediatek,mt8173-apmixedsys  >hdmi-phy@10209100mediatek,mt8173-hdmi-phy  $zpll_refhdmitx_dig_cts Zokay><mipi-dphy@10215000mediatek,mt8173-mipi-tx !Pz  mipi_tx0_pll Zdisabled>6mipi-dphy@10216000mediatek,mt8173-mipi-tx !`z  mipi_tx1_pll Zdisabled>7interrupt-controller@10221000 arm,gic-400 @ "" "@ "`   > auxadc@11001000mediatek,mt8173-auxadc zmain>serial@11002000*mediatek,mt8173-uartmediatek,mt6577-uart   Sz$ baudbusZokayserial@11003000*mediatek,mt8173-uartmediatek,mt6577-uart 0 Tz% baudbus Zdisabledserial@11004000*mediatek,mt8173-uartmediatek,mt6577-uart @ Uz& baudbus Zdisabledserial@11005000*mediatek,mt8173-uartmediatek,mt6577-uart P Vz' baudbus Zdisabledi2c@11007000mediatek,mt8173-i2c  pp Lz  maindmadefault+ Zdisabledi2c@11008000mediatek,mt8173-i2c  p Mz  maindmadefault+Zokayda9211@68 dlg,da9211 hregulatorsBUCKAVBUCKA `0C#'*BUCKBVBUCKB `0-'i2c@11009000mediatek,mt8173-i2c  p Nz  maindmadefault+ Zdisabledspi@1100a000mediatek,mt8173-spi+  nz 4 \parent-clksel-clkspi-clkZokaydefaultthermal@1100b000-mediatek,mt8173-thermal  Fz thermauxadcCSgscalibration-data>spi@1100d000mediatek,mt8173-nor z! rspisf+ Zdisabledi2c@11010000mediatek,mt8173-i2c  p Oz  maindmadefault+ Zdisabledi2c@11011000mediatek,mt8173-i2c  p Pz  maindmadefault + Zdisabledi2c@11012000mediatek,mt8173-hdmi-ddc Q  zddc-i2ci2c@11013000mediatek,mt8173-i2c  0p Rz#  maindmadefault!+ Zdisabledaudio-controller@11220000mediatek,mt8173-afe-pcm " Pz  d e y  binfra_sys_audio_clktop_pdn_audiotop_pdn_aud_intbusbck0bck1i2s0_mi2s1_mi2s2_mi2s3_mi2s3_b m n  mmc@11230000mediatek,mt8173-mmc # Gz _ sourcehclkZokaydefaultstate_uhs"#<$H%Ummc@11240000mediatek,mt8173-mmc $ Hz R sourcehclkZokaydefaultstate_uhs&'ct <(H)mmc@11250000mediatek,mt8173-mmc % Iz R sourcehclk Zdisabledmmc@11260000mediatek,mt8173-mmc & Jz u sourcehclk Zdisabledusb@11271000mediatek,mt8173-mtu3  '0( macippc @*+,z ^   *sys_ckref_ckwakeup_deb_p0wakeup_deb_p1+vZokay-./otgdefaultid_floatid_ground001xhci@11270000mediatek,mt8173-xhci 'mac s z ^ sys_ckref_ckZokay-2usb-phy@11290000mediatek,mt8173-u3phy )+vZokayusb-phy@11290800 )zrefZokay>*usb-phy@11290900 ) z refZokay>+usb-phy@11291000 )zrefZokay>,clock-controller@14000000mediatek,mt8173-mmsyssyscon  Uׄ>3rdma@14001000-mediatek,mt8173-mdp-rdmamediatek,mt8173-mdp z334 5rdma@14002000mediatek,mt8173-mdp-rdma  z334 rsz@14003000mediatek,mt8173-mdp-rsz 0z3rsz@14004000mediatek,mt8173-mdp-rsz @z3rsz@14005000mediatek,mt8173-mdp-rsz Pz3wdma@14006000mediatek,mt8173-mdp-wdma `z3 4 wrot@14007000mediatek,mt8173-mdp-wrot pz3 4 wrot@14008000mediatek,mt8173-mdp-wrot z3 4 ovl@1400c000mediatek,mt8173-disp-ovl  z34 ovl@1400d000mediatek,mt8173-disp-ovl  z34 rdma@1400e000mediatek,mt8173-disp-rdma  z34 rdma@1400f000mediatek,mt8173-disp-rdma  z34 rdma@14010000mediatek,mt8173-disp-rdma  z34 wdma@14011000mediatek,mt8173-disp-wdma  z34 wdma@14012000mediatek,mt8173-disp-wdma   z34 color@14013000mediatek,mt8173-disp-color 0 z3color@14014000mediatek,mt8173-disp-color @ z3aal@14015000mediatek,mt8173-disp-aal P z3gamma@14016000mediatek,mt8173-disp-gamma ` z3merge@14017000mediatek,mt8173-disp-merge pz3split@14018000mediatek,mt8173-disp-split z3split@14019000mediatek,mt8173-disp-split z3ufoe@1401a000mediatek,mt8173-disp-ufoe  z3dsi@1401b000mediatek,mt8173-dsi  z3$3%6enginedigitalhs6'dphy Zdisableddsi@1401c000mediatek,mt8173-dsi  z3&3'7enginedigitalhs7'dphy Zdisableddpi@1401d000mediatek,mt8173-dpi  z3(3)pixelenginepllZokayportendpoint18>=pwm@1401e0002mediatek,mt8173-disp-pwmmediatek,mt6595-disp-pwm Az3!3 mainmmZokaydefault9pwm@1401f0002mediatek,mt8173-disp-pwmmediatek,mt6595-disp-pwm Az3#3"mainmm Zdisabledmutex@14020000mediatek,mt8173-disp-mutex  z3larb@14021000mediatek,mt8173-smi-larb L:z33apbsmi>smi@14022000mediatek,mt8173-smi-common  z33apbsmi>:od@14023000mediatek,mt8173-disp-od 0z3hdmi@14025000mediatek,mt8173-hdmi P  z3,3-3.3/pixelpllbclkspdifdefault;<'hdmiY3  s<Zokayports+port@0 endpoint1=>8port@1 endpoint1>>Clarb@14027000mediatek,mt8173-smi-larb pL:z3232apbsmi>clock-controller@15000000mediatek,mt8173-imgsyssyscon >?larb@15001000mediatek,mt8173-smi-larb L:z??apbsmi>clock-controller@16000000mediatek,mt8173-vdecsyssyscon >@vcodec@16000000mediatek,mt8173-vcodec-dec  0@Phpx  @4 4!4%4&4'4"4#4$5@z > l W M i NZvcodecpllunivpll_d2clk_cci400_selvdec_selvdecpllvencpllvenc_lt_selvdec_bus_clk_srclarb@16010000mediatek,mt8173-smi-larb L:z@@apbsmi>clock-controller@18000000mediatek,mt8173-vencsyssyscon >Alarb@18001000mediatek,mt8173-smi-larb L:zAAapbsmi>vcodec@18002000mediatek,mt8173-vcodec-enc     4`4a4b4c4d4i4j4k4l4m4n4444444445 z P X ? i2venc_sel_srcvenc_selvenc_lt_sel_srcvenc_lt_selclock-controller@19000000!mediatek,mt8173-vencltsyssyscon >Blarb@19001000mediatek,mt8173-smi-larb L:zBBapbsmi>memory@40000000memory @chosenconnectorhdmi-connectornhdmidportendpoint1C>>extcon_iddiglinux,extcon-usb-gpio t>/regulator@0regulator-fixed usb_vbusLK@LK@ w|>2regulator@1regulator-fixedvbusLK@LK@ w |>. compatibleinterrupt-parent#address-cells#size-cellsmodelovl0ovl1rdma0rdma1rdma2wdma0wdma1color0color1split0split1dpi0dsi0dsi1mdp_rdma0mdp_rdma1mdp_rsz0mdp_rsz1mdp_rsz2mdp_wdma0mdp_wrot0mdp_wrot1serial0serial1serial2serial3cpudevice_typeregenable-methodcpu-idle-states#cooling-cellsphandleentry-methodlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usarm,psci-suspend-paramcpu_suspendcpu_offcpu_on#clock-cellsclock-frequencyclock-output-namespolling-delay-passivepolling-delaythermal-sensorssustainable-powertemperaturehysteresistripcooling-devicecontributionrangesalignmentno-mapinterrupts#reset-cellsmediatek,pctl-regmappins-are-numberedgpio-controller#gpio-cellsinterrupt-controller#interrupt-cellspinmuxinput-enablebias-pull-downbias-disableoutput-lowbias-pull-updrive-strength#power-domain-cellsclocksclock-namesinfracfgreg-namesresetsreset-namespower-domainsregulator-compatibleregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-enable-ramp-delaystatusmemory-regionmediatek,larbs#iommu-cellsmediatek,ibiasmediatek,ibias_up#phy-cells#io-channel-cellsclock-divpinctrl-namespinctrl-0regulator-min-microampregulator-max-microampmediatek,pad-select#thermal-sensor-cellsmediatek,auxadcmediatek,apmixedsysnvmem-cellsnvmem-cell-namesassigned-clocksassigned-clock-parentspinctrl-1bus-widthmax-frequencycap-mmc-highspeedmediatek,hs200-cmd-int-delaymediatek,hs400-cmd-int-delaymediatek,hs400-cmd-resp-sel-risingvmmc-supplyvqmmc-supplynon-removablecap-sd-highspeedsd-uhs-sdr25cd-gpiosphysmediatek,syscon-wakeupvusb33-supplyvbus-supplyextcondr_modemediatek,enable-wakeuppinctrl-2assigned-clock-ratesiommusmediatek,larbmediatek,vpuphy-namesremote-endpoint#pwm-cellsmediatek,smimediatek,syscon-hdmilabelid-gpioenable-active-high