68(:(hisilicon,hi6220-hikeyhisilicon,hi6220 +7HiKey Development Boardpsci arm,psci-0.2=smccpus+cpu-mapcluster0core0Dcore1Dcore2Dcore3Dcluster1core0Dcore1Dcore2Dcore3D idle-statesHpscicpu-sleeparm,idle-stateUf} cluster-sleeparm,idle-stateUf} cpu@0arm,cortex-a53arm,armv8cpupsci   %7F V7cpu@1arm,cortex-a53arm,armv8cpupsci  F cpu@2arm,cortex-a53arm,armv8cpupsci  F cpu@3arm,cortex-a53arm,armv8cpupsci  F cpu@100arm,cortex-a53arm,armv8cpupsci F cpu@101arm,cortex-a53arm,armv8cpupsci F cpu@102arm,cortex-a53arm,armv8cpupsci F cpu@103arm,cortex-a53arm,armv8cpupsci F  l2-cache0cache l2-cache1cachecpu_opp_tableoperating-points-v2p opp00{ eހ opp01{ހ opp02{+s@ opp03{98p` opp04{GKP interrupt-controller@f6801000 arm,gic-400@ @ `   timerarm,armv8-timer 0   soc simple-bus+sram@fff80000!hisilicon,hi6220-sramctrlsyscon ao_ctrl@f7800000hisilicon,hi6220-aoctrlsyscon sys_ctrl@f7030000 hisilicon,hi6220-sysctrlsyscon media_ctrl@f4410000"hisilicon,hi6220-mediactrlsysconATpm_ctrl@f7032000hisilicon,hi6220-pmctrlsyscon acpu_sctrl@f6504000#hisilicon,hi6220-acpu-sctrlsysconP@Xmedianoc_ade@f4520000sysconR@Sstub_clockhisilicon,hi6220-stub-clk mbox-tx  uart@f8015000arm,pl011arm,primecellP $$$uartclkapb_pclkuart@f7111000arm,pl011arm,primecell %uartclkapb_pclk+default 9CokJ)Zрbluetooth ti,wl1835-st o ext_clockuart@f7112000arm,pl011arm,primecell  &uartclkapb_pclk+default9Cok |LS-UART0uart@f7113000arm,pl011arm,primecell0 'uartclkapb_pclk+default9Cok |LS-UART1uart@f7114000arm,pl011arm,primecell@ (uartclkapb_pclk+default9 Cdisableddma@f7370000hisilicon,k3-dma-1.07  T  hi6220_dmaCokOtimer@f8008000arm,sp804arm,primecelltimer1timer2apb_pclkrtc@f8003000arm,pl031arm,primecell0  % apb_pclkrtc@f8004000arm,pl031arm,primecell@ & apb_pclkpinmux@f7010000pinctrl-single|+ pPX`hpx!+08Jz~+default9 !"#$+gpio-range1boot_sel_pmx_funcR emmc_pmx_funcPR  $:sd_pmx_func0R  ?sd_pmx_idle0R  Bsdio_pmx_func0R(,048<Gsdio_pmx_idle0R(,048<Jisp_pmx_funcR$(,048<@DHLPTX\`hkadc_ssi_pmx_funcRh!codec_clk_pmx_funcRl"codec_pmx_func Rptx|fm_pmx_func Rbt_pmx_func Rpwm_in_pmx_funcR#bl_pwm_pmx_funcR$uart0_pmx_funcRuart1_pmx_func Ruart2_pmx_func Ruart3_pmx_func Ruart4_pmx_func Ruart5_pmx_funcRi2c0_pmx_funcR/i2c1_pmx_funcR1i2c2_pmx_funcR3spi0_pmx_func R,pinmux@f7010800pinconf-single+ +default9%&'()boot_sel_cfg_funcRfp%hkadc_ssi_cfg_funcRlfp&emmc_clk_cfg_funcRf p;emmc_cfg_funcHR  $(fp<emmc_rst_cfg_funcR,fp=sd_clk_cfg_funcR f0p@sd_clk_cfg_idleR fpCsd_cfg_func(R f pAsd_cfg_idle(R fpDsdio_clk_cfg_funcR4f pHsdio_clk_cfg_idleR4fpKsdio_cfg_func(R8<@DHfpIsdio_cfg_idle(R8<@DHfpLisp_cfg_func1xR(,048<@DHLPX\`dfpisp_cfg_idle1R48fpisp_cfg_func2RTfpcodec_clk_cfg_funcRpfp'codec_clk_cfg_idleRpfpcodec_cfg_func1Rtfpcodec_cfg_func2Rx|fpcodec_cfg_idle2Rx|fpfm_cfg_func Rfpbt_cfg_func Rfpbt_cfg_idle Rfppwm_in_cfg_funcRfp(bl_pwm_cfg_funcRfp)uart0_cfg_func1Rfpuart0_cfg_func2Rfpuart1_cfg_func1Rfpuart1_cfg_func2Rfpuart2_cfg_func Rfpuart3_cfg_func Rfpuart4_cfg_func Rfpuart5_cfg_funcRfpi2c0_cfg_funcRfp0i2c1_cfg_funcRfp2i2c2_cfg_funcRfp4spi0_cfg_func Rfp-pinmux@f8001800pinconf-singlex+ +default9*rstout_n_cfg_funcRfp*pmu_peri_en_cfg_funcRfpsysclk0_en_cfg_funcRfpjtag_tdo_cfg_funcR f prf_reset_cfg_funcRptfpgpio@f8011000arm,pl061arm,primecell 4 apb_pclkOPWR_HOLDDSI_SELUSB_HUB_RESET_NUSB_SELHDMI_PDWL_REG_ONPWRON_DET5V_HUB_EN5gpio@f8012000arm,pl061arm,primecell  5 apb_pclk:SD_DETHDMI_INTPMU_IRQ_NWL_HOST_WAKENCNCNCBT_REG_ONgpio@f8013000arm,pl061arm,primecell0 6 apb_pclkBGPIO-AGPIO-BGPIO-CGPIO-DGPIO-EUSB_ID_DETUSB_VBUS_DETGPIO-Hgpio@f8014000arm,pl061arm,primecell@ 7+P apb_pclk%GPIO3_0NCNCNCWLAN_ACTIVENCNCugpio@f7020000arm,pl061arm,primecell 8+X apb_pclk?USER_LED1USER_LED2USER_LED3USER_LED4SD_SELNCNCBT_ACTIVEtgpio@f7021000arm,pl061arm,primecell 9+` apb_pclk?NCNC[UART1_RxD][UART1_TxD][AUX_SSI1]NC[PCM_CLK][PCM_FS]gpio@f7022000arm,pl061arm,primecell  :+h apb_pclk=[SPI0_DIN][SPI0_DOUT][SPI0_CS][SPI0_SCLK]NCNCNCGPIO-G.gpio@f7023000arm,pl061arm,primecell0 ;+p apb_pclk$NCNCNCNC[PCM_DI][PCM_DO]NCNCgpio@f7024000arm,pl061arm,primecell@ < +x+ apb_pclkNC[CEC_CLK_19_2MHZ]NCgpio@f7025000arm,pl061arm,primecellP =+ apb_pclk'GPIO-JGPIO-LNCNCNCNC[ISP_CCLK0]gpio@f7026000arm,pl061arm,primecell` > ++ apb_pclk?BOOT_SEL[ISP_CCLK1]GPIO-IGPIO-KNCNC[I2C2_SDA][I2C2_SCL]gpio@f7027000arm,pl061arm,primecellp ? ++ apb_pclk"[I2C3_SDA][I2C3_SCL]NCNCNCgpio@f7028000arm,pl061arm,primecell @ +!++ apb_pclk8[BT_PCM_XFS][BT_PCM_DI][BT_PCM_DO]NCNCNCNCGPIO-Fgpio@f7029000arm,pl061arm,primecell A+0 apb_pclkh[UART0_RX][UART0_TX][BT_UART1_CTS][BT_UART1_RTS][BT_UART1_RX][BT_UART1_TX][UART0_CTS][UART0_RTS]gpio@f702a000arm,pl061arm,primecell B+8 apb_pclkZ[UART0_RxD][UART0_TxD][I2C0_SCL][I2C0_SDA][I2C1_SCL][I2C1_SDA][I2C2_SCL][I2C2_SDA]gpio@f702b000arm,pl061arm,primecell C0+J+z+~ apb_pclk NCgpio@f702c000arm,pl061arm,primecell D+ apb_pclkgpio@f702d000arm,pl061arm,primecell E+ apb_pclkgpio@f702e000arm,pl061arm,primecell F+ apb_pclkgpio@f702f000arm,pl061arm,primecell G+ apb_pclkspi@f7106000arm,pl022arm,primecell` 2 apb_pclk+default9,-  .Coki2c@f7100000snps,designware-i2c , ,+default9/0Coki2c@f7101000snps,designware-i2c -,+default912Coki2c@f7102000snps,designware-i2c  .,+default934Cok+adv7533@39 adi,adv75339  +54Bports+port@0endpointS6Wport@2endpointS7Pusbphyhisilicon,hi6220-usb-phycn8y9usb@f72c0000hisilicon,hi6220-usb,9 usb2-phyotgotg< Mmailbox@f7510000hisilicon,hi6220-mbox Q ^dwmmc0@f723d000hisilicon,hi6220-dw-mshc# Hciubiureset+default9:;<= %>dwmmc1@f723e000hisilicon,hi6220-dw-mshcy# I+ciubiureset +defaultidle 9?@A 1BCD;M^kxE%F dwmmc2@f723f000hisilicon,hi6220-dw-mshc# Jciubiureset +defaultidle 9GHI 1JKL %MN+wlcore@2 ti,wl1835 tsensor@0,f7030700hisilicon,tsensor  thermal_clkQi2s@f7118000hisilicon,hi6210-i2s { 8dacodeci2s-baseOOrxtxBportsport@0vendpointSPi2s7thermal-zonescls0d 0Qtripstrip-point@0@Lpassivetrip-point@1@$LpassiveRcooling-mapsmap0WR \ade@f4100000hisilicon,hi6220-adex kade_baseuST sTTT(clk_ade_coreclk_codec_jpegclk_ade_pixJTTZu**CokportendpointSUVdsi@f4107800hisilicon,hi6220-dsixTpclkCokports+port@0endpointSVUport@1endpoint@0SW6debug@f6590000&arm,coresight-cpu-debugarm,primecellY; apb_pclkDdebug@f6592000&arm,coresight-cpu-debugarm,primecellY ; apb_pclkDdebug@f6594000&arm,coresight-cpu-debugarm,primecellY@; apb_pclkDdebug@f6596000&arm,coresight-cpu-debugarm,primecellY`; apb_pclkDdebug@f65d0000&arm,coresight-cpu-debugarm,primecell]; apb_pclkDdebug@f65d2000&arm,coresight-cpu-debugarm,primecell] ; apb_pclkDdebug@f65d4000&arm,coresight-cpu-debugarm,primecell]@; apb_pclkDdebug@f65d6000&arm,coresight-cpu-debugarm,primecell]`; apb_pclkD funnel@f6401000#arm,coresight-funnelarm,primecell@X apb_pclkports+port@0endpointSY[port@1endpointSZbetf@f6402000 arm,coresight-tmcarm,primecell@ X apb_pclkports+port@0endpointS[Yport@1endpointS\]replicatorarm,coresight-replicatorX apb_pclkports+port@0endpointS]\port@1endpointS^`port@2endpointS_aetr@f6404000 arm,coresight-tmcarm,primecell@@X apb_pclkports+port@0endpointS`^tpiu@f6405000!arm,coresight-tpiuarm,primecell@PX apb_pclkports+port@0endpointSa_funnel@f6501000#arm,coresight-funnelarm,primecellPX apb_pclkports+port@0endpointSbZport@1endpointSckport@2endpointSdlport@3endpointSemport@4endpointSfnport@5endpointSgoport@6endpointShpport@7endpointSiqport@8endpointSjretm@f659c000"arm,coresight-etm4xarm,primecellYX apb_pclkDportendpointSkcetm@f659d000"arm,coresight-etm4xarm,primecellYX apb_pclkDportendpointSldetm@f659e000"arm,coresight-etm4xarm,primecellYX apb_pclkDportendpointSmeetm@f659f000"arm,coresight-etm4xarm,primecellYX apb_pclkDportendpointSnfetm@f65dc000"arm,coresight-etm4xarm,primecell]X apb_pclkDportendpointSogetm@f65dd000"arm,coresight-etm4xarm,primecell]X apb_pclkDportendpointSphetm@f65de000"arm,coresight-etm4xarm,primecell]X apb_pclkDportendpointSqietm@f65df000"arm,coresight-etm4xarm,primecell]X apb_pclkD portendpointSrjaliases/soc/uart@f8015000/soc/uart@f7111000/soc/uart@f7112000/soc/uart@f7113000chosenserial3:115200n8memory@0memory` `A"reserved-memory+ramoops@0x21f00000ramoops!linux,cmashared-dma-poolreboot-mode-syscon@5f01000sysconsimple-mfdreboot-modesyscon-reboot-modewfU!wfU1wfUregulator@0regulator-fixed?SYS_5VNLK@fLK@~sregulator@1regulator-fixed?VDD_3V3N2Zf2Z~sMregulator@2regulator-fixed?5V_HUBNLK@fLK@~ 5s8wl1835-pwrseqmmc-pwrseq-simple 5 ext_clock  Nleds gpio-ledsuser_led4 |user_led4 vt heartbeatuser_led3 |user_led3 vtmmc0user_led2 |user_led2 vtmmc1user_led1 |user_led1 vtcpu0wlan_active_led |wifi_active vuphy0txoffbt_active_led |bt_active vthci0rxoffpmic@f8000000hisilicon,hi655x-pmic regulatorsLDO2 ?LDO2_2V8N&%f0xLDO7 ?LDO7_SDIONw@f2ZxELDO10 ?LDO10_2V85Nw@f-hFLDO13 ?LDO13_1V8Njf0xLDO14 ?LDO14_2V8N&%f0xLDO15 ?LDO15_1V8Njf0~xLDO17 ?LDO17_2V5N&%f0xLDO19 ?LDO19_3V0Nw@f-h>LDO21 ?LDO21_1V8N-PfxLDO22 ?LDO22_1V2N fO~xfirmwareopteelinaro,optee-tz=smcsound_cardaudio-graph-card5v compatibleinterrupt-parent#address-cells#size-cellsmodelmethodcpuentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usphandlewakeup-latency-usdevice_typeregenable-methodnext-level-cacheclocksoperating-points-v2cooling-min-levelcooling-max-level#cooling-cellscpu-idle-statesdynamic-power-coefficientopp-sharedopp-hzopp-microvoltclock-latency-ns#interrupt-cellsinterrupt-controllerinterruptsranges#clock-cells#reset-cellshisilicon,hi6220-clk-srammbox-namesmboxesclock-namespinctrl-namespinctrl-0statusassigned-clocksassigned-clock-ratesenable-gpioslabel#dma-cellsdma-channelsdma-requestsdma-no-ccidma-type#pinctrl-cells#gpio-range-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,gpio-range#pinctrl-single,gpio-range-cellspinctrl-single,pinspinctrl-single,bias-pulldownpinctrl-single,bias-pulluppinctrl-single,drive-strengthgpio-controller#gpio-cellsgpio-line-namesgpio-rangesbus-idenable-dmanum-cscs-gpiosi2c-sda-hold-time-nspd-gpiosadi,dsi-lanes#sound-dai-cellsremote-endpoint#phy-cellsphy-supplyhisilicon,peripheral-sysconphysphy-namesdr_modeg-rx-fifo-sizeg-np-tx-fifo-sizeg-tx-fifo-size#mbox-cellsresetsreset-namescap-mmc-highspeednon-removablebus-widthvmmc-supplypinctrl-1card-detect-delaycap-sd-highspeedsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50vqmmc-supplydisable-wpcd-gpiosmmc-pwrseq#thermal-sensor-cellsdmasdma-nameshisilicon,sysctrl-syscondai-formatpolling-delaypolling-delay-passivesustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicereg-nameshisilicon,noc-syscondma-coherentslave-modeserial0serial1serial2serial3stdout-pathrecord-sizeconsole-sizeftrace-sizereusablelinux,cma-defaultoffsetmode-normalmode-bootloadermode-recoveryregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onregulator-always-onvin-supplygpioreset-gpiospost-power-on-delay-mspower-off-delay-uslinux,default-triggerdefault-statepmic-gpiosregulator-enable-ramp-delaydais