}8v(mvl+hisilicon,hi3660-hikey960hisilicon,hi3660 + 7HiKey960psci arm,psci-0.2=smccpus+cpu-mapcluster0core0Dcore1Dcore2Dcore3Dcluster1core0Dcore1Dcore2Dcore3D cpu@0arm,cortex-a53arm,armv8HcpuTXpscif w cpu@1arm,cortex-a53arm,armv8HcpuTXpscif w cpu@2arm,cortex-a53arm,armv8HcpuTXpscif w cpu@3arm,cortex-a53arm,armv8HcpuTXpscif w cpu@100arm,cortex-a73arm,armv8HcpuTXpscif  w cpu@101arm,cortex-a73arm,armv8HcpuTXpscif  w cpu@102arm,cortex-a73arm,armv8HcpuTXpscif  w cpu@103arm,cortex-a73arm,armv8HcpuTXpscif  w  idle-statespscicpu-naparm,idle-statecpu-sleeparm,idle-state(F  cluster-sleep-0arm,idle-stateN  cluster-sleep-1arm,idle-stateN l2-cache0cache l2-cache1cache interrupt-controller@e82b0000 arm,gic-400@T++ +@ +`   pmuarm,armv8-pmuv3` ' timerarm,armv8-timer 0   soc simple-bus+:crg_ctrl@fff35000 hisilicon,hi3660-crgctrlsysconTPAcrg_rst_controllerhisilicon,hi3660-resetN[pctrl@e8a09000hisilicon,hi3660-pctrlsysconT蠐 Acrg_ctrl@fff34000 hisilicon,hi3660-pmuctrlsysconT@Asctrl@fff0a000hisilicon,hi3660-sctrlsysconTA0iomcu@ffd7e000hisilicon,hi3660-iomcusysconTAresethisilicon,hi3660-reset[Ntimer@fff14000arm,sp804arm,primecellT@01k   rtimer1timer2apb_pclki2c@ffd71000snps,designware-i2cT v+~k  defaultokayLS-I2C0i2c@ffd72000snps,designware-i2cT  w+~k  defaultokayadv7533@39ok adi,adv7533T9ports+port@0Tport@1Ti2c@fdf0c000snps,designware-i2cT Q+~k7 xdefault disabledi2c@fdf0b000snps,designware-i2cT :+~k6 `defaultokayLS-I2C1serial@fdf02000arm,pl011arm,primecellT  Jkhruartclkapb_pclkdefault disabledserial@fdf00000arm,pl011arm,primecellT Kk99ruartclkapb_pclkdefault disabledserial@fdf03000arm,pl011arm,primecellT0 Lk:ruartclkapb_pclkdefault ! disabledserial@ffd74000arm,pl011arm,primecellT@ rkruartclkapb_pclkdefault"#okay LS-UART0serial@fdf01000arm,pl011arm,primecellT Mk;;ruartclkapb_pclkdefault$%okaybluetooth ti,wl1837-st &-serial@fdf05000arm,pl011arm,primecellTP Nk<<ruartclkapb_pclkdefault'( disabledserial@fff32000arm,pl011arm,primecellT  Ok ruartclkapb_pclkdefault)*okay LS-UART1dma@fdf30000hisilicon,k3-dma-1.0T  k> hi3660_dmartc@fff04000arm,pl031arm,primecellT@ .k rapb_pclkgpio@e8a0b000arm,pl061arm,primecellT蠰 T%5A+k rapb_pclkLMTP901[PMU0_SSI][PMU1_SSI][PMU2_SSI][PMU0_CLKOUT][JTAG_TCK][JTAG_TMS]gpio@e8a0c000arm,pl061arm,primecellT U%5A+k  rapb_pclkCM[JTAG_TRST_N][JTAG_TDI][JTAG_TDO]NCNC[I2C3_SCL][I2C3_SDA]NCgpio@e8a0d000arm,pl061arm,primecellT V%5A+k! rapb_pclkGMNCNCNCGPIO-JGPIO_020_HDMI_SELGPIO-LGPIO_022_UFSBUCK_INT_NGPIO-Ggpio@e8a0e000arm,pl061arm,primecellT W%5A+k" rapb_pclkJM[CSI0_MCLK][CSI1_MCLK]NC[I2C2_SCL][I2C2_SDA][I2C3_SCL][I2C3_SDA]NCgpio@e8a0f000arm,pl061arm,primecellT X%5A+k# rapb_pclkAMNCNCPWR_BTN_NGPIO_035_PMU2_ENGPIO_036_USB_HUB_RESETNCNCNCDgpio@e8a10000arm,pl061arm,primecellT Y%5A+&k$ rapb_pclkQMGPIO-HGPIO_041_HDMI_PDTP904TP905NCNCGPIO_046_HUB_VDD33_ENGPIO_047_PMU1_ENgpio@e8a11000arm,pl061arm,primecellT Z%5A+.k% rapb_pclkAMNCNCNCGPIO_051_WIFI_ENGPIO-I[SD_DAT1][SD_DAT2][UART1_RXD]Fgpio@e8a12000arm,pl061arm,primecellT  [%5A+6k& rapb_pclkyM[UART1_TXD][UART0_CTS][UART0_RTS][UART0_RXD][UART0_TXD][SOC_BT_UART4_CTS_N][SOC_BT_UART4_RTS_N][SOC_BT_UART4_RXD]gpio@e8a13000arm,pl061arm,primecellT0 \%5A+>k' rapb_pclk?M[SOC_BT_UART4_TXD]NC[PMU_HKADC_SSI]NCGPIO_068_SELNCNCNCgpio@e8a14000arm,pl061arm,primecellT@ ]%5A+Fk( rapb_pclkMNCNCNCGPIO-KNCNCNCNCgpio@e8a15000arm,pl061arm,primecellTP ^%5A+Nk) rapb_pclkMNCNCNCNCNCNCNCNCgpio@e8a16000arm,pl061arm,primecellT` _%5A+Vk* rapb_pclk$MNC[PCIE_PERST_N]NCNCNCNCNCNC5gpio@e8a17000arm,pl061arm,primecellTp `%5 A+^+ek+ rapb_pclkMNCNCNCNCgpio@e8a18000arm,pl061arm,primecellT血 a%5A+fk, rapb_pclkMNCNCNCNCNCNCNCNCgpio@e8a19000arm,pl061arm,primecellT衐 b%5A+nk- rapb_pclkMNCNCNCNCNCNCNCNCgpio@e8a1a000arm,pl061arm,primecellT衠 c%5A+vk. rapb_pclk'MNCNCNCNCNCNCGPIO_126_BT_ENTP902&gpio@e8a1b000arm,pl061arm,primecellT衰 d%5k/ rapb_pclkMgpio@e8a1c000arm,pl061arm,primecellT e%5k0 rapb_pclkMgpio@ff3b4000arm,pl061arm,primecellT;@ f%5A,k1 rapb_pclkmM[UFS_REF_CLK][UFS_RST_N][SPI1_SCLK][SPI1_DIN][SPI1_DOUT][SPI1_CS]GPIO_150_USER_LED1GPIO_151_USER_LED24gpio@ff3b5000arm,pl061arm,primecellT;P g%5A,k2 rapb_pclkMNCNCNCNCgpio@e8a1f000arm,pl061arm,primecellT h%5A-k3 rapb_pclk@M[SD_CLK][SD_CMD][SD_DATA0][SD_DATA1][SD_DATA2][SD_DATA3]gpio@e8a20000arm,pl061arm,primecellT i%5A.k4 rapb_pclk^M[WL_SDIO_CLK][WL_SDIO_CMD][WL_SDIO_DATA0][WL_SDIO_DATA1][WL_SDIO_DATA2][WL_SDIO_DATA3]gpio@fff0b000arm,pl061arm,primecellT j%5A/k0 rapb_pclkdM[GPIO_176_PMU_PWR_HOLD]NA[SYSCLK_EN]GPIO_179_WL_WAKEUP_APGPIO_180_HDMI_INTNAGPIO-F[I2C0_SCL]@gpio@fff0c000arm,pl061arm,primecellT k%5A/k0 rapb_pclk^M[I2C0_SDA][I2C1_SCL][I2C1_SDA][I2C1_SCL][I2C1_SDA]GPIO_189_USER_LED3GPIO_190_USER_LED4Egpio@fff0d000arm,pl061arm,primecellT l%5A/ k0 rapb_pclktM[PCM_DI][PCM_DO][PCM_CLK][PCM_FS][GPIO_196_I2S2_DI][GPIO_197_I2S2_DO][GPIO_198_I2S2_XCLK][GPIO_199_I2S2_XFS]gpio@fff0e000arm,pl061arm,primecellT m%5 A//k0 rapb_pclkzMNCNCGPIO_202_VBUS_TYPECGPIO_203_SD_DETGPIO_204_PMU12_IRQ_NGPIO_205_WIFI_ACTIVEGPIO_206_USBSW_SELGPIO_207_BT_ACTIVE6gpio@fff0f000arm,pl061arm,primecellT n%5A/k0 rapb_pclkLMGPIO-AGPIO-BGPIO-CGPIO-DGPIO-E[PCIE_CLKREQ_N][PCIE_WAKE_N][SPI0_CLK]gpio@fff10000arm,pl061arm,primecellT o%5A/$k0 rapb_pclkBM[SPI0_DIN][SPI0_DOUT][SPI0_CS]GPIO_219_CC_INTNCNC[PMU_INT]2gpio@fff1d000arm,pl061arm,primecellT %5k0 rapb_pclkMspi@ffd68000arm,pl022arm,primecellTր+ tk rapb_pclkdefault1] d2okayLS-SPI0spi@ff3b3000arm,pl022arm,primecellT;0+ 8k5 rapb_pclkdefault3] d4okayHS-SPI1pcie@f4000000hisilicon,kirin960-pcie@T? mdbiapbphyconfigw+Hpci:(kRSQP:rpcie_phy_refpcie_auxpcie_apb_phypcie_apb_syspcie_aclk 5dwmmc1@ff37f000+hisilicon,hi3660-dw-mshcT7 kKrciubiu~0 reset %6.0default 789JWdqokay:;slot@0Tdwmmc2@ff3ff000hisilicon,hi3660-dw-mshcT? kLrciubiu resetdefault <=>ok?+wlcore@2 ti,wl1837T @watchdog@e8a06000arm,sp805-wdtarm,primecellT` ,k  rapb_pclkwatchdog@e8a07000arm,sp805-wdtarm,primecellTp -k  rapb_pclktsensor@fff30000hisilicon,hi3660-tsensorT gpio-rangeApinmux@e896c000pinctrl-singleT! ? \AAt+pmu_pmx_func v csi0_pwd_n_pmx_funcvDcsi1_pwd_n_pmx_funcvLisp0_pmx_funcvXdhisp1_pmx_funcv\lppwr_key_pmx_funcvBi2c3_pmx_funcv,0i2c4_pmx_funcvpcie_perstn_pmx_funcv\usbhub5734_pmx_funcv uart0_pmx_funcvuart1_pmx_func vuart2_pmx_func v uart3_pmx_func v"uart4_pmx_func v$uart5_pmx_func v'uart6_pmx_func v)cam0_rst_pmx_funcvcam1_rst_pmx_funcv$pinmux@ff37e000pinctrl-singleT7! ?\A-sd_pmx_func0v 7pinmux@ff3b6000pinctrl-singleT;`0! ?\A ,ufs_pmx_funcvspi3_pmx_func v 3pinmux@ff3fd000pinctrl-singleT?! ?\A.sdio_pmx_func0v <pinmux@fff11000pinctrl-singleT! ?\A*/i2s2_pmx_func vDHLPslimbus_pmx_funcv,0i2c0_pmx_funcvi2c1_pmx_funcv i2c7_pmx_funcv$(pcie_pmx_funcvspi2_pmx_func v1i2s0_pmx_func v48<@pinmux@e896c800pinconf-singleT! pmu_cfg_func v  i2c3_cfg_funcv8<csi0_pwd_n_cfg_funcvPcsi1_pwd_n_cfg_funcvXisp0_cfg_funcvdptisp1_cfg_funcvhx|pwr_key_cfg_funcvCuart1_cfg_func vuart2_cfg_func v!uart5_cfg_func v(cam0_rst_cfg_funcvuart0_cfg_funcvuart6_cfg_func v*uart3_cfg_func v#uart4_cfg_func v%cam1_rst_cfg_funcv0pinmux@ff3b6800pinconf-singleT;h! ufs_cfg_funcv0spi3_cfg_funcvpinmux@ff3fd800pinconf-singleT?! sdio_clk_cfg_funcv=sdio_cfg_func(v >pinmux@ff37e800pinconf-singleT7! sd_clk_cfg_funcv8sd_cfg_func(v 9pinmux@fff11800pinconf-singleT! i2c0_cfg_funcv i2c1_cfg_funcv$(i2c7_cfg_funcv,0slimbus_cfg_funcv48i2s0_cfg_func v@DHLi2s2_cfg_func vPTX\pcie_cfg_funcvspi2_cfg_func vusb_cfg_funcvaliases/soc/dwmmc1@ff37f000/soc/dwmmc2@ff3ff000/soc/serial@fdf02000/soc/serial@fdf00000/soc/serial@fdf03000/soc/serial@ffd74000 /soc/serial@fdf01000/soc/serial@fdf05000/soc/serial@fff32000chosen$serial6:115200n8memory@0HmemoryTreserved-memory+:ramoops@32000000ramoopsT20<Ireboot-mode-syscon@32100000sysconsimple-mfdT2reboot-modesyscon-reboot-modeU\wfUhwfUxwfUkeys gpio-keysdefaultBCpower D GPIO Powertleds gpio-ledsuser_led1 user_led1 4 heartbeatuser_led2 user_led2 4mmc0user_led3 user_led3 Eoffuser_led4 user_led4 Ecpu0wlan_active_led wifi_active 6phy0txoffbt_active_led bt_active 6 hci0-poweroffpmic@fff34000hisilicon,hi6421v530-pmicT@regulatorsLDO3 VOUT3_1V85w@!xLDO9VOUT9_1V8_2V952Z;LDO11VOUT11_1V8_2V952ZLDO15 VOUT15_3V0-0xLDO16 VOUT16_2V95-h:wlan-en-1-8vregulator-fixedwlan-en-regulatorw@w@ DFIpZ?firmwareopteelinaro,optee-tz=smc compatibleinterrupt-parent#address-cells#size-cellsmodelmethodcpudevice_typeregenable-methodnext-level-cachecpu-idle-statesphandleentry-methodarm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uslocal-timer-stop#interrupt-cellsinterrupt-controllerinterruptsinterrupt-affinityranges#clock-cells#reset-cellshisi,rst-sysconclocksclock-namesclock-frequencyresetspinctrl-namespinctrl-0statuslabeladi,dsi-lanesenable-gpiosmax-speed#dma-cellsdma-channelsdma-requestsdma-min-chandma-no-ccidma-typegpio-controller#gpio-cellsgpio-rangesgpio-line-namesnum-cscs-gpiosreg-namesbus-rangenum-lanesinterrupt-map-maskinterrupt-mapreset-gpioscd-invertednum-slotsbus-widthdisable-wpcap-sd-highspeedsupports-highspeedcard-detect-delayreset-namescd-gpioshisilicon,peripheral-sysconsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplykeep-power-in-suspendbroken-cdti,non-removable#thermal-sensor-cells#pinctrl-single,gpio-range-cells#pinctrl-cells#gpio-range-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,gpio-rangepinctrl-single,pinspinctrl-single,bias-pulldownpinctrl-single,bias-pulluppinctrl-single,drive-strengthmshc1mshc2serial0serial1serial2serial3serial4serial5serial6stdout-pathrecord-sizeconsole-sizeftrace-sizeoffsetmode-normalmode-bootloadermode-recoverywakeup-sourcelinux,codelinux,default-triggerdefault-stateregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-boot-onregulator-always-ongpiostartup-delay-usenable-active-high