!aH8()RTSM_VE_AEMv8A arm,rtsm_ve,aemv8aarm,vexpress"1chosenaliases6=/smb@8000000/motherboard/iofpga@3,00000000/uart@900006E/smb@8000000/motherboard/iofpga@3,00000000/uart@a00006M/smb@8000000/motherboard/iofpga@3,00000000/uart@b00006U/smb@8000000/motherboard/iofpga@3,00000000/uart@c0000cpus"1cpu@0]cpu arm,armv8i mspin-table{cpu@1]cpu arm,armv8i mspin-table{cpu@2]cpu arm,armv8i mspin-table{cpu@3]cpu arm,armv8i mspin-table{l2-cache0cachememory@80000000]memory iinterrupt-controller@2c001000%arm,cortex-a15-gicarm,cortex-a9-gic"@i,, ,@ ,`   timerarm,armv8-timer0   pmuarm,armv8-pmuv30<=>?smb@8000000 simple-bus"1x  ?            !!""##$$%%&&''(())**motherboardrs1arm,vexpress,v2m-p1simple-bus"1flash@0,00000000arm,vexpress-flashcfi-flashi!vram@2,00000000arm,vexpress-vram i ethernet@2,02000000smsc,lan91c111 iclk24mhz fixed-clock,n6 9v2m:clk24mhzrefclk1mhz fixed-clock,B@9v2m:refclk1mhzrefclk32khz fixed-clock,9v2m:refclk32khziofpga@3,00000000 simple-bus"1 sysreg@10000arm,vexpress-sysregiL\sysctl@20000arm,sp810arm,primecelli horefclktimclkapb_pclk,09timerclken0timerclken1timerclken2timerclken3 {aaci@40000arm,pl041arm,primecelli h oapb_pclkmmci@50000arm,pl180arm,primecelli   homclkapb_pclkkmi@60000arm,pl050arm,primecelli hoKMIREFCLKapb_pclkkmi@70000arm,pl050arm,primecelli hoKMIREFCLKapb_pclkuart@90000arm,pl011arm,primecelli houartclkapb_pclkuart@a0000arm,pl011arm,primecelli houartclkapb_pclkuart@b0000arm,pl011arm,primecelli houartclkapb_pclkuart@c0000arm,pl011arm,primecelli houartclkapb_pclkwdt@f0000arm,sp805arm,primecellihowdogclkapb_pclktimer@110000arm,sp804arm,primecellihotimclken1timclken2apb_pclktimer@120000arm,sp804arm,primecellihotimclken1timclken2apb_pclkrtc@170000arm,pl031arm,primecellih oapb_pclkclcd@1f0000arm,pl111arm,primecelli combinedh oclcdclkapb_pclk portendpoint  ' panel panel-dpiportendpoint  panel-timing_AIU0bhltvirtio-block@130000 virtio,mmioi*v2m-3v3regulator-fixed3V32Z2Zmccarm,vexpress,config-busoscclk1arm,vexpress-oscjep, 9v2m:oscclk1 resetarm,vexpress-resetmuxfpgaarm,vexpress-muxfpgashutdownarm,vexpress-shutdownrebootarm,vexpress-reboot dvimodearm,vexpress-dvimode  modelcompatibleinterrupt-parent#address-cells#size-cellsserial0serial1serial2serial3device_typeregenable-methodcpu-release-addrnext-level-cachephandle#interrupt-cellsinterrupt-controllerinterruptsclock-frequencyrangesinterrupt-map-maskinterrupt-maparm,v2m-memory-mapbank-width#clock-cellsclock-output-namesgpio-controller#gpio-cellsclocksclock-namesassigned-clocksassigned-clock-parentscd-gpioswp-gpiosmax-frequencyvmmc-supplyinterrupt-namesarm,pl11x,framebuffermemory-regionmax-memory-bandwidthremote-endpointarm,pl11x,tft-r0g0b0-padshactivehback-porchhfront-porchhsync-lenvactivevback-porchvfront-porchvsync-lenregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onarm,vexpress,config-bridgearm,vexpress-sysreg,funcfreq-range