*8(((n',Xunlong Orange Pi Plus)2xunlong,orangepi-plusallwinner,sun8i-h3chosen=serial0:115200n8aliasesI/soc/serial@01c28000memoryQmemory]cpuscpu@02arm,cortex-a7Qcpu]cpu@12arm,cortex-a7Qcpu]cpu@22arm,cortex-a7Qcpu]cpu@32arm,cortex-a7Qcpu]timer2arm,armv7-timer0a   clockslosc24M_clks 2fixed-clockn6osc24Mosc32k_clks 2fixed-clockosc32kclk@01c20000s2allwinner,sun8i-a23-pll1-clk]pll1pll5_clks 2fixed-clockpll5clk@01c20028s2allwinner,sun6i-a31-pll6-clk]( pll6pll6x2pll6d2_clks2fixed-factor-clockpll6d2  clk@c01c20044s2allwinner,sun6i-a31-pll6-clk]D pll8pll8x2  cpu_clk@01c20050s2allwinner,sun4i-a10-cpu-clk]Pcpuaxi_clk@01c20050s2allwinner,sun4i-a10-axi-clk]Paxiahb1_clk@01c20054s2allwinner,sun6i-a31-ahb1-clk]Tahb1ahb2_clk@01c2005cs2allwinner,sun8i-h3-ahb2-clk]\ ahb2  apb1_clk@01c20054s2allwinner,sun4i-a10-apb0-clk]Tapb1  apb2_clk@01c20058s2allwinner,sun4i-a10-apb1-clk]Xapb2  clk@01c20060s!2allwinner,sun8i-h3-bus-gates-clk]` ahb1ahb2apb1apb2  #$%()+,456@AEHLMN`abpqrstbus_cebus_dmabus_mmc0bus_mmc1bus_mmc2bus_nandbus_sdrambus_gmacbus_tsbus_hstimerbus_spi0bus_spi1bus_otgbus_otg_ehci0bus_ehci1bus_ehci2bus_ehci3bus_otg_ohci0bus_ohci1bus_ohci2bus_ohci3bus_vebus_lcd0bus_lcd1bus_deintbus_csibus_tvebus_hdmibus_debus_gpubus_msgboxbus_spinlockbus_codecbus_spdifbus_piobus_thsbus_i2s0bus_i2s1bus_i2s2bus_i2c0bus_i2c1bus_i2c2bus_uart0bus_uart1bus_uart2bus_uart3bus_scrbus_ephybus_dbgclk@01c20088s2allwinner,sun4i-a10-mmc-clk] mmc0mmc0_outputmmc0_sampleclk@01c2008cs2allwinner,sun4i-a10-mmc-clk] mmc1mmc1_outputmmc1_sampleclk@01c20090s2allwinner,sun4i-a10-mmc-clk] mmc2mmc2_outputmmc2_sampleclk@01c2015cs2allwinner,sun8i-a23-mbus-clk]\mbussoc 2simple-busldma-controller@01c020002allwinner,sun8i-h3-dma]  a2mmc@01c0f0002allwinner,sun5i-a13-mmc] ahbmmcoutputsampleahb a<okay default$0:Cmmc@01c100002allwinner,sun5i-a13-mmc]  ahbmmcoutputsample ahb a= disabledmmc@01c110002allwinner,sun5i-a13-mmc]  ahbmmcoutputsample ahb a> disabledpinctrl@01c208002allwinner,sun8i-h3-pinctrl]a EO_kuart0@0PA4PA5uart0mmc0@0PF0PF1PF2PF3PF4PF5mmc0mmc0_cd_pin@0PF6gpio_inmmc1@0PG0PG1PG2PG3PG4PG5mmc1ahci_pwr_pin@0PB8 gpio_outusb0_vbus_pin@0PB9 gpio_outusb1_vbus_pin@0PH6 gpio_outusb2_vbus_pin@0PH3 gpio_outreset@01c202c02allwinner,sun6i-a31-ahb1-reset] reset@01c202d0 2allwinner,sun6i-a31-clock-reset]reset@01c202d8 2allwinner,sun6i-a31-clock-reset]timer@01c20c002allwinner,sun4i-a10-timer] awatchdog@01c20ca02allwinner,sun6i-a31-wdt]  aserial@01c280002snps,dw-apb-uart]€ aprxtxokay defaultserial@01c284002snps,dw-apb-uart]„ aqrxtx disabledserial@01c288002snps,dw-apb-uart]ˆ arrxtx disabledserial@01c28c002snps,dw-apb-uart]Œ as  rxtx disabledinterrupt-controller@01c81000%2arm,cortex-a7-gicarm,cortex-a15-gic ] @ ` k a rtc@01f000002allwinner,sun6i-a31-rtc]Ta()ahci-5v2regulator-fixed defaultahci-5vLK@,LK@DVi disabledusb0-vbus2regulator-fixed default usb0-vbusLK@,LK@Vi  disabledusb1-vbus2regulator-fixed default usb1-vbusLK@,LK@DVi disabledusb2-vbus2regulator-fixed default usb2-vbusLK@,LK@DVi disabledvcc3v02regulator-fixedvcc3v0-,-vcc3v32regulator-fixedvcc3v32Z,2Zvcc5v02regulator-fixedvcc5v0LK@,LK@ #address-cells#size-cellsinterrupt-parentmodelcompatiblestdout-pathserial0device_typereginterruptsranges#clock-cellsclock-frequencyclock-output-nameslinux,phandleclocksclock-divclock-multclock-namesclock-indicesresets#dma-cellsreset-namesstatuspinctrl-namespinctrl-0vmmc-supplybus-widthcd-gpioscd-invertedgpio-controller#gpio-cellsinterrupt-controller#interrupt-cellsallwinner,pinsallwinner,functionallwinner,driveallwinner,pull#reset-cellsreg-shiftreg-io-widthdmasdma-namesregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onenable-active-highgpio