s8z(zpgoogle,veyron-mickey-rev8google,veyron-mickey-rev7google,veyron-mickey-rev6google,veyron-mickey-rev5google,veyron-mickey-rev4google,veyron-mickey-rev3google,veyron-mickey-rev2google,veyron-mickey-rev1google,veyron-mickey-rev0google,veyron-mickeygoogle,veyronrockchip,rk3288&7Google Mickeychosenaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000memorymemoryarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12`@p@ @OOa sB@ ~ ' 9  K 0 $@29EKcpu@501cpuarm,cortex-a12EKcpu@502cpuarm,cortex-a12EKcpu@503cpuarm,cortex-a12EKamba arm,amba-busSdma-controller@ff250000arm,pl330arm,primecell%@Z2 eapb_pclkEKdma-controller@ff600000arm,pl330arm,primecell`@Z2 eapb_pclk qdisableddma-controller@ffb20000arm,pl330arm,primecell@Z2 eapb_pclkEGKGreserved-memorySdma-unusable@fe000000oscillator fixed-clockxn6xin24mE K timerarm,armv7-timer0   xn6timer@ff810000rockchip,rk3288-timer  H 2 a etimerpclkdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshcр 2Drvebiuciuciu-driveciu-sample  @ qdisableddwmmc@ff0d0000rockchip,rk3288-dw-mshcр 2Eswebiuciuciu-driveciu-sample ! @qokay"8 CQ[default i sdwmmc@ff0e0000rockchip,rk3288-dw-mshcр 2Ftxebiuciuciu-driveciu-sample "@ qdisableddwmmc@ff0f0000rockchip,rk3288-dw-mshcр 2Guyebiuciuciu-driveciu-sample #@qokay8CQ[default isaradc@ff100000rockchip,saradc $2I[esaradcapb_pclk qdisabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi2ARespiclkapb_pclk  txrx ,[defaulti qdisabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi2BSespiclkapb_pclk txrx -[defaulti qdisabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi2CTespiclkapb_pclktxrx .[defaulti !"qokay i2c@ff140000rockchip,rk3288-i2c >ei2c2M[defaulti#qokayx02Hdtpm@20infineon,slb9645tt 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cpu_very_hot_limit_cpu3 gpu_thermald.tripsgpu_alert0ppassiveE4K4gpu_crit_ criticalcooling-mapsmap04 tsadc@ff280000rockchip,rk3288-tsadc( %2HZetsadcapb_pclk tsadc-apb[initdefaultsleepi56(52Hsqokay_vE.K.ethernet@ff290000rockchip,rk3288-gmac) macirq782fgc]Mestmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB stmmaceth qdisabledusb@ff500000 generic-ehciP 2eusbhost8usb qdisabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 2eotghost9 usb2-phy qdisabledusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 2eotghost@@  : usb2-phyqokayz]usb@ff5c0000 generic-ehci\ 2eusbhost qdisabledi2c@ff650000rockchip,rk3288-i2ce <ei2c2L[defaulti;qokayx02Hdpmic@1brockchip,rk808xin32kwifibt_32kin&<[default i=>?,M[gs@A AE]K]regulatorsDCDC_REG1vdd_arm q ,qEKregulator-state-memADCDC_REG2vdd_gpu 5,qregulator-state-memZrB@DCDC_REG3 vcc135_ddrregulator-state-memZDCDC_REG4vcc_18w@w@EKregulator-state-memZrw@LDO_REG3vdd_10B@B@regulator-state-memZrB@LDO_REG7 vdd10_lcdB@B@SWITCH_REG1 vcc33_lcdE\K\regulator-state-memALDO_REG8w@w@ vcc18_lcdi2c@ff660000rockchip,rk3288-i2cf =ei2c2N[defaultiB qdisabledx02H pwm@ff680000rockchip,rk3288-pwmh[defaultiC2^epwm qdisabledpwm@ff680010rockchip,rk3288-pwmh[defaultiD2^epwmqokaypwm@ff680020rockchip,rk3288-pwmh [defaultiE2^epwm qdisabledpwm@ff680030rockchip,rk3288-pwmh0[defaultiF2^epwm qdisabledbus_intmem@ff700000 mmio-sramp Spsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsEKpower-controller!rockchip,rk3288-power-controllerh EJKJpd_vio 2chgfdehilkjpd_hevc 2oppd_video 2pd_gpu 2syscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv7Hjk$#gׄeрxhрxhEKsyscon@ff770000rockchip,rk3288-grfsysconwE7K7watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt2p Oqokaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif ehclkmclk2TGtx U[defaultiH7 qdisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s UGGtxrxei2s_hclki2s_clki2s_clk_out2Rq[defaultiIqokaycypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 2}eaclkhclksclkapb_pclk crypto-rstqokayvop@ff930000rockchip,rk3288-vop 2eaclk_vopdclk_vophclk_vopJ def axiahbdclk-KqokayportE K endpoint@04LEPKPiommu@ff930300rockchip,iommu  vopb_mmuJ DqokayEKKKvop@ff940000rockchip,rk3288-vop 2eaclk_vopdclk_vophclk_vopJ  axiahbdclk-M qdisabledportE K endpoint@04NEQKQiommu@ff940300rockchip,iommu  vopl_mmuJ D qdisabledEMKMhdmi@ff980000rockchip,rk3288-dw-hdmi7 g2hm eiahbisfrJ qokayQOportsportendpoint@04PELKLendpoint@14QENKNinterrupt-controller@ffc01000 arm,gic-400]r  @ `   EKefuse@ffb40000rockchip,rockchip-efuse 2q epclk_efusecpu_leakage@17phyrockchip,rk3288-usb-phy7qokayusb-phy0 2]ephyclkE:K:usb-phy142^ephyclkE8K8usb-phy2H2_ephyclkE9K9pinctrlrockchip,rk3288-pinctrl7S[defaultsleepiRRgpio0@ff750000rockchip,gpio-banku Q2@]rE<K<gpio1@ff780000rockchip,gpio-bankx R2A]rgpio2@ff790000rockchip,gpio-banky S2B]rE[K[gpio3@ff7a0000rockchip,gpio-bankz T2C]rgpio4@ff7b0000rockchip,gpio-bank{ U2D]rE`K`gpio5@ff7c0000rockchip,gpio-bank| V2E]rgpio6@ff7d0000rockchip,gpio-bank} W2F]rgpio7@ff7e0000rockchip,gpio-bank~ X2G]rEAKAgpio8@ff7f0000rockchip,gpio-bank Y2H]rhdmihdmi-ddc SSpower-hdmi-on SEbKbpcfg-pull-upETKTpcfg-pull-downEWKWpcfg-pull-noneESKSpcfg-pull-none-12ma EVKVsleepglobal-pwroffSERKRddrio-pwroffSddr0-retentionTddr1-retentionTi2c0i2c0-xfer SSE;K;i2c1i2c1-xfer SSE#K#i2c2i2c2-xfer  S SEBKBi2c3i2c3-xfer SSE$K$i2c4i2c4-xfer SSE%K%i2c5i2c5-xfer SSE&K&i2s0i2s0-bus`SSSSSSEIKIsdmmcsdmmc-clkSsdmmc-cmdTsdmmc-cdTsdmmc-bus1Tsdmmc-bus4@TTTTsdio0sdio0-bus1Tsdio0-bus4@UUUUEKsdio0-cmdUEKsdio0-clkUE K sdio0-cdTsdio0-wpTsdio0-pwrTsdio0-bkpwrTsdio0-intTwifienable-hSE_K_bt-enable-lSE^K^sdio1sdio1-bus1Tsdio1-bus4@TTTTsdio1-cdTsdio1-wpTsdio1-bkpwrTsdio1-intTsdio1-cmdTsdio1-clkSsdio1-pwr Temmcemmc-clkUEKemmc-cmdUEKemmc-pwr Temmc-bus1Temmc-bus4@TTTTemmc-bus8UUUUUUUUEKemmc-reset SEZKZspi0spi0-clk TEKspi0-cs0 TEKspi0-txTEKspi0-rxTEKspi0-cs1Tspi1spi1-clk TEKspi1-cs0 TEKspi1-rxTEKspi1-txTEKspi2spi2-cs1Tspi2-clkTEKspi2-cs0TE"K"spi2-rxTE!K!spi2-tx TE K uart0uart0-xfer TSE'K'uart0-ctsTE(K(uart0-rtsSE)K)uart1uart1-xfer T SE*K*uart1-cts Tuart1-rts Suart2uart2-xfer TSE+K+uart3uart3-xfer TSE,K,uart3-cts Tuart3-rts Suart4uart4-xfer  T SE-K-uart4-ctsTuart4-rtsStsadcotp-gpio SE5K5otp-out SE6K6pwm0pwm0-pinSECKCpwm1pwm1-pinSEDKDpwm2pwm2-pinSEEKEpwm3pwm3-pinSEFKFgmacrgmii-pinsSSSSVVVVSSS VVSSrmii-pinsSSSSSSSSSSspdifspdif-tx SEHKHpcfg-pull-none-drv-8maEUKUpcfg-pull-up-drv-8mapcfg-output-highpcfg-output-lowbuttonspwr-key-lTEXKXpmicpmic-int-lTE=K=dvs-1 WE>K>dvs-2WE?K?rebootap-warm-reset-h SEYKYrecovery-switchrec-mode-l Ttpmtpm-int-hSwrite-protectfw-wp-apSgpio-keys gpio-keys[defaultiXpowerPower < td*gpio-restart gpio-restart < [defaultiY:emmc-pwrseqmmc-pwrseq-emmciZ[default C[ EKio-domains"rockchip,rk3288-io-voltage-domain7O@Ydr@@\sdio-pwrseqmmc-pwrseq-simple2] eext_clock[defaulti^_ C`E K vcc-5vregulator-fixedvcc_5vLK@LK@EaKavcc33-sysregulator-fixed vcc33_sys2Z2ZEKvcc50-hdmiregulator-fixed vcc50_hdmia A [defaultibvcc33_ioregulator-fixed vcc33_ioE@K@ #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2device_typereginterruptsinterrupt-affinityenable-methodrockchip,pmuresetsoperating-points#cooling-cellsclock-latencyclockscpu0-supplylinux,phandleranges#dma-cellsclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredportsclock-freq-min-maxfifo-depthbroken-cdbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablenum-slotspinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplycap-mmc-highspeedrockchip,default-sample-phasedisable-wp#io-channel-cellsdmasdma-namesrx-sample-delay-nsi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedreg-shiftreg-io-widthassigned-clocksassigned-clock-ratespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfphysphy-namesneeds-reset-on-resumedr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmaassigned-clock-parentsrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc7-supplyvcc8-supplyvddio-supplydvs-gpiosvcc11-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltregulator-suspend-mem-disabled#pwm-cells#power-domain-cells#reset-cells#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channelspower-domainsiommusremote-endpoint#iommu-cellsddc-i2c-businterrupt-controller#interrupt-cells#phy-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowlabellinux,codedebounce-intervalgpio-key,wakeuppriorityreset-gpiosbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyvin-supplyenable-active-highgpio