8x<(xKgoogle,veyron-brain-rev0google,veyron-braingoogle,veyronrockchip,rk3288& 7Google Brainchosenaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000memorymemoryarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12`@p@ @OOa sB@ ~ ' 9  K 0 $@29EKcpu@501cpuarm,cortex-a12EKcpu@502cpuarm,cortex-a12EKcpu@503cpuarm,cortex-a12EKamba arm,amba-busSdma-controller@ff250000arm,pl330arm,primecell%@Z2 eapb_pclkEKdma-controller@ff600000arm,pl330arm,primecell`@Z2 eapb_pclk qdisableddma-controller@ffb20000arm,pl330arm,primecell@Z2 eapb_pclkEDKDreserved-memorySdma-unusable@fe000000oscillator fixed-clockxn6xin24mE K timerarm,armv7-timer0   xn6timer@ff810000rockchip,rk3288-timer  H 2 a etimerpclkdisplay-subsystemrockchip,display-subsystem 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2eusbhost5usbqokayusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 2eotghost6 usb2-phyqokayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 2eotghost @@ 7 usb2-phyqokayz$]usb@ff5c0000 generic-ehci\ 2eusbhost qdisabledi2c@ff650000rockchip,rk3288-i2ce <ei2c2L[defaulti8qokayx?2Wdpmic@1brockchip,rk808xin32kwifibt_32kin&9[default i:;<;\jv=> >EZKZregulatorsDCDC_REG1vdd_arm q# ;qEKregulator-state-memPDCDC_REG2vdd_gpu 5#;qregulator-state-memiB@DCDC_REG3 vcc135_ddrregulator-state-memiDCDC_REG4vcc_18 w@#w@EKregulator-state-memiw@LDO_REG3vdd_10 B@#B@regulator-state-memiB@LDO_REG7 vdd10_lcd B@#B@regulator-state-memPSWITCH_REG1 vcc33_lcdEYKYregulator-state-memPSWITCH_REG2 vcc18_hdmii2c@ff660000rockchip,rk3288-i2cf =ei2c2N[defaulti?qokayx?2W pwm@ff680000rockchip,rk3288-pwmh[defaulti@2^epwm qdisabledpwm@ff680010rockchip,rk3288-pwmh[defaultiA2^epwmqokaypwm@ff680020rockchip,rk3288-pwmh [defaultiB2^epwm qdisabledpwm@ff680030rockchip,rk3288-pwmh0[defaultiC2^epwm qdisabledbus_intmem@ff700000 mmio-sramp Spsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsEKpower-controller!rockchip,rk3288-power-controllerh$ EGKGpd_vio 2chgfdehilkjpd_hevc 2oppd_video 2pd_gpu 2syscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv4Hjk$#gׄeрxhрxhEKsyscon@ff770000rockchip,rk3288-grfsysconwE4K4watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt2p Oqokaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif ehclkmclk2TD"tx U[defaultiE4 qdisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s UDD"txrxei2s_hclki2s_clk2R[defaultiF qdisabledcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 2}eaclkhclksclkapb_pclk !crypto-rstqokayvop@ff930000rockchip,rk3288-vop 2eaclk_vopdclk_vophclk_vop.G def !axiahbdclk<HqokayportE K endpoint@0CIEMKMiommu@ff930300rockchip,iommu  vopb_mmu.G SqokayEHKHvop@ff940000rockchip,rk3288-vop 2eaclk_vopdclk_vophclk_vop.G  !axiahbdclk<J qdisabledportE K endpoint@0CKENKNiommu@ff940300rockchip,iommu  vopl_mmu.G S qdisabledEJKJhdmi@ff980000rockchip,rk3288-dw-hdmi4 g2hm eiahbisfr.G qokay`Lportsportendpoint@0CMEIKIendpoint@1CNEKKKinterrupt-controller@ffc01000 arm,gic-400l  @ `   EKefuse@ffb40000rockchip,rockchip-efuse 2q epclk_efusecpu_leakage@17phyrockchip,rk3288-usb-phy4qokayusb-phy0 2]ephyclkE7K7usb-phy142^ephyclkE5K5usb-phy2H2_ephyclkE6K6pinctrlrockchip,rk3288-pinctrl4S[defaultsleepiO-Ogpio0@ff750000rockchip,gpio-banku Q2@lE9K9gpio1@ff780000rockchip,gpio-bankx R2Algpio2@ff790000rockchip,gpio-banky S2BlEXKXgpio3@ff7a0000rockchip,gpio-bankz T2Clgpio4@ff7b0000rockchip,gpio-bank{ U2DlE]K]gpio5@ff7c0000rockchip,gpio-bank| V2Elgpio6@ff7d0000rockchip,gpio-bank} W2Flgpio7@ff7e0000rockchip,gpio-bank~ X2GlE>K>gpio8@ff7f0000rockchip,gpio-bank Y2Hlhdmihdmi-ddc PPvcc50-hdmi-enPE_K_pcfg-pull-upEQKQpcfg-pull-downETKTpcfg-pull-noneEPKPpcfg-pull-none-12ma ESKSsleepglobal-pwroffPEOKOddrio-pwroffPddr0-retentionQddr1-retentionQi2c0i2c0-xfer PPE8K8i2c1i2c1-xfer PPE#K#i2c2i2c2-xfer  P PE?K?i2c3i2c3-xfer PPE$K$i2c4i2c4-xfer PPE%K%i2c5i2c5-xfer PPE&K&i2s0i2s0-bus`PPPPPPEFKFsdmmcsdmmc-clkPsdmmc-cmdQsdmmc-cdQsdmmc-bus1Qsdmmc-bus4@QQQQsdio0sdio0-bus1Qsdio0-bus4@RRRREKsdio0-cmdREKsdio0-clkRE K sdio0-cdQsdio0-wpQsdio0-pwrQsdio0-bkpwrQsdio0-intQwifienable-hPE\K\bt-enable-lPE[K[sdio1sdio1-bus1Qsdio1-bus4@QQQQsdio1-cdQsdio1-wpQsdio1-bkpwrQsdio1-intQsdio1-cmdQsdio1-clkPsdio1-pwr Qemmcemmc-clkREKemmc-cmdREKemmc-pwr Qemmc-bus1Qemmc-bus4@QQQQemmc-bus8RRRRRRRREKemmc-reset PEWKWspi0spi0-clk QEKspi0-cs0 QEKspi0-txQEKspi0-rxQEKspi0-cs1Qspi1spi1-clk QEKspi1-cs0 QEKspi1-rxQEKspi1-txQEKspi2spi2-cs1Qspi2-clkQEKspi2-cs0QE"K"spi2-rxQE!K!spi2-tx QE K uart0uart0-xfer QPE'K'uart0-ctsQE(K(uart0-rtsPE)K)uart1uart1-xfer Q PE*K*uart1-cts Quart1-rts Puart2uart2-xfer QPE+K+uart3uart3-xfer QPE,K,uart3-cts Quart3-rts Puart4uart4-xfer  Q PE-K-uart4-ctsQuart4-rtsPtsadcotp-gpio PE2K2otp-out PE3K3pwm0pwm0-pinPE@K@pwm1pwm1-pinPEAKApwm2pwm2-pinPEBKBpwm3pwm3-pinPECKCgmacrgmii-pinsPPPPSSSSPPP SSPPrmii-pinsPPPPPPPPPPspdifspdif-tx PEEKEpcfg-pull-none-drv-8maERKRpcfg-pull-up-drv-8mapcfg-output-highpcfg-output-low buttonspwr-key-lQEUKUpmicpmic-int-lQE:K:dvs-1 TE;K;dvs-2TE<K<rebootap-warm-reset-h PEVKVrecovery-switchrec-mode-l Qtpmtpm-int-hPwrite-protectfw-wp-apPusb-hostusb2-pwr-en PE`K`gpio-keys gpio-keys[defaultiUpowerPower 9t'd9gpio-restart gpio-restart 9 [defaultiVIemmc-pwrseqmmc-pwrseq-emmciW[default RX EKio-domains"rockchip,rk3288-io-voltage-domain4^=hs==Ysdio-pwrseqmmc-pwrseq-simple2Z eext_clock[defaulti[\ R]E K vcc-5vregulator-fixedvcc_5v LK@#LK@E^K^vcc33-sysregulator-fixed vcc33_sys 2Z#2Z^EKvcc50-hdmiregulator-fixed vcc50_hdmi^ >[defaulti_vcc33_ioregulator-fixed vcc33_ioE=K=vcc5-host2-regulatorregulator-fixed 9 [defaulti` vcc5_host2 #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2device_typereginterruptsinterrupt-affinityenable-methodrockchip,pmuresetsoperating-points#cooling-cellsclock-latencyclockscpu0-supplylinux,phandleranges#dma-cellsclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredportsclock-freq-min-maxfifo-depthbroken-cdbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablenum-slotspinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplycap-mmc-highspeedrockchip,default-sample-phasedisable-wpmmc-hs200-1_8v#io-channel-cellsdmasdma-namesrx-sample-delay-nsi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedreg-shiftreg-io-widthassigned-clocksassigned-clock-ratespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfphysphy-namesneeds-reset-on-resumedr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmaassigned-clock-parentsrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplydvs-gpiosregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltregulator-suspend-mem-disabled#pwm-cells#power-domain-cells#reset-cells#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channelspower-domainsiommusremote-endpoint#iommu-cellsddc-i2c-businterrupt-controller#interrupt-cells#phy-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowlabellinux,codedebounce-intervalgpio-key,wakeuppriorityreset-gpiosbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyvin-supplyenable-active-highgpio