z8s@(}s#radxa,rock2-squarerockchip,rk3288&7Radxa Rock 2 Squarechosen=serial2:115200n8aliasesI/ethernet@ff290000S/i2c@ff650000X/i2c@ff140000]/i2c@ff660000b/i2c@ff150000g/i2c@ff160000l/i2c@ff170000q/dwmmc@ff0f0000w/dwmmc@ff0c0000}/dwmmc@ff0d0000/dwmmc@ff0e0000/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000memorymemoryarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12 `@p@ @OOa sB@ ~ ' 9  K 0 !0@>EQWcpu@501cpuarm,cortex-a12 QWcpu@502cpuarm,cortex-a12 QWcpu@503cpuarm,cortex-a12 QWamba arm,amba-bus_dma-controller@ff250000arm,pl330arm,primecell%@f> qapb_pclkQWdma-controller@ff600000arm,pl330arm,primecell`@f> qapb_pclk }disableddma-controller@ffb20000arm,pl330arm,primecell@f> qapb_pclkQFWFreserved-memory_dma-unusable@fe000000oscillator fixed-clockn6xin24mQ W timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H > a qtimerpclkdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshcр >Drvqbiuciuciu-driveciu-sample  @}okay);FPdefault^ htdwmmc@ff0d0000rockchip,rk3288-dw-mshcр >Eswqbiuciuciu-driveciu-sample ! @ }disableddwmmc@ff0e0000rockchip,rk3288-dw-mshcр >Ftxqbiuciuciu-driveciu-sample "@ }disableddwmmc@ff0f0000rockchip,rk3288-dw-mshcр >Guyqbiuciuciu-driveciu-sample #@}okay;FPdefault ^hsaradc@ff100000rockchip,saradc $>I[qsaradcapb_pclk }disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi>ARqspiclkapb_pclk  txrx ,Pdefault^ }disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi>BSqspiclkapb_pclk txrx -Pdefault^ }disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi>CTqspiclkapb_pclktxrx .Pdefault^ !"# }disabledi2c@ff140000rockchip,rk3288-i2c >qi2c>MPdefault^$ }disabledi2c@ff150000rockchip,rk3288-i2c ?qi2c>OPdefault^% }disabledi2c@ff160000rockchip,rk3288-i2c @qi2c>PPdefault^& }disabledi2c@ff170000rockchip,rk3288-i2c Aqi2c>QPdefault^'}okayQNWNserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7>MUqbaudclkapb_pclkPdefault^( }disabledserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8>NVqbaudclkapb_pclkPdefault^) }disabledserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9>OWqbaudclkapb_pclkPdefault^*}okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :>PXqbaudclkapb_pclkPdefault^+ }disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;>QYqbaudclkapb_pclkPdefault^, }disabledthermal-zonesreserve_thermal-cpu_thermald-tripscpu_alert0ppassiveQ.W.cpu_alert1$passiveQ/W/cpu_crit_ criticalcooling-mapsmap0. "map1/ "gpu_thermald-tripsgpu_alert0ppassiveQ0W0gpu_crit_ criticalcooling-mapsmap00 "tsadc@ff280000rockchip,rk3288-tsadc( %>HZqtsadcapb_pclk  1tsadc-apbPinitdefaultsleep^1=2G1Qgs}okay~Q-W-ethernet@ff290000rockchip,rk3288-gmac) macirq38>fgc]Mqstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac B 1stmmaceth}ok4inputrgmii 5Pdefault^67 8% ;'u0PY0usb@ff500000 generic-ehciP >qusbhostb9gusb}okayusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T >qotgqhostb: gusb2-phy }disabledusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X >qotgqotgy@@ b; gusb2-phy }disabledusb@ff5c0000 generic-ehci\ >qusbhost }disabledi2c@ff650000rockchip,rk3288-i2ce <qi2c>LPdefault^<}okayact8846@5aactive-semi,act8846Z=>====regulatorsREG1VCC_DDR*OBOZREG2VCC_IO*2ZB2ZZQWREG3VDD_LOG*B@BB@ZREG4VCC_20*BZQ>W>REG5 VCCIO_SD*2ZB2ZZQWREG6 VDD10_LCD*B@BB@ZREG7 VCCA_CODEC*2ZB2ZZREG8VCCA_TP*2ZB2ZZREG9 VCCIO_PMU*2ZB2ZZQ5W5REG10VDD_10*B@BB@ZREG11VCC_18*w@Bw@ZREG12 VCC18_LCD*w@Bw@Zsyr827@40silergy,syr827@nZ,vdd_cpu* PBp@=QWsyr828@41silergy,syr828AnZ,* PBpvdd_gpu@=hym8563@51haoyu,hym8563Qxin32k&?Pdefault^@i2c@ff660000rockchip,rk3288-i2cf =qi2c>NPdefault^A }disabledpwm@ff680000rockchip,rk3288-pwmhPdefault^B>^qpwm }disabledpwm@ff680010rockchip,rk3288-pwmhPdefault^C>^qpwm }disabledpwm@ff680020rockchip,rk3288-pwmh Pdefault^D>^qpwm }disabledpwm@ff680030rockchip,rk3288-pwmh0Pdefault^E>^qpwm }disabledbus_intmem@ff700000 mmio-sramp _psmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsQWpower-controller!rockchip,rk3288-power-controllerQIWIpd_vio >chgfdehilkjpd_hevc >oppd_video >pd_gpu >syscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv3Hjk$#gׄeрxhрxhQWsyscon@ff770000rockchip,rk3288-grfsysconwQ3W3watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt>p O}okaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif qhclkmclk>TFtx UPdefault^G3}okayQYWYi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s UFFtxrxqi2s_hclki2s_clk>RPdefault^H+F }disabledcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 >}qaclkhclksclkapb_pclk  1crypto-rst}okayvop@ff930000rockchip,rk3288-vop >qaclk_vopdclk_vophclk_vop`I  def 1axiahbdclknJ}okayportQ W endpoint@0uKQOWOiommu@ff930300rockchip,iommu  vopb_mmu`I }okayQJWJvop@ff940000rockchip,rk3288-vop >qaclk_vopdclk_vophclk_vop`I   1axiahbdclknL}okayportQ W endpoint@0uMQPWPiommu@ff940300rockchip,iommu  vopl_mmu`I }okayQLWLhdmi@ff980000rockchip,rk3288-dw-hdmi3 g>hm qiahbisfr`I }okayNportsportendpoint@0uOQKWKendpoint@1uPQMWMinterrupt-controller@ffc01000 arm,gic-400  @ `   QWefuse@ffb40000rockchip,rockchip-efuse >q qpclk_efusecpu_leakage@17phyrockchip,rk3288-usb-phy3}okayusb-phy0 >]qphyclkQ;W;usb-phy14>^qphyclkQ9W9usb-phy2H>_qphyclkQ:W:pinctrlrockchip,rk3288-pinctrl3_gpio0@ff750000rockchip,gpio-banku Q>@Q?W?gpio1@ff780000rockchip,gpio-bankx R>Agpio2@ff790000rockchip,gpio-banky S>Bgpio3@ff7a0000rockchip,gpio-bankz T>CQVWVgpio4@ff7b0000rockchip,gpio-bank{ U>DQ8W8gpio5@ff7c0000rockchip,gpio-bank| V>Egpio6@ff7d0000rockchip,gpio-bank} W>Fgpio7@ff7e0000rockchip,gpio-bank~ X>GQ\W\gpio8@ff7f0000rockchip,gpio-bank Y>HQWWWhdmihdmi-ddc QQpcfg-pull-upQRWRpcfg-pull-downpcfg-pull-noneQQWQpcfg-pull-none-12ma" QSWSsleepglobal-pwroffQddrio-pwroffQddr0-retentionRddr1-retentionRi2c0i2c0-xfer QQQ<W<i2c1i2c1-xfer QQQ$W$i2c2i2c2-xfer  Q QQAWAi2c3i2c3-xfer QQQ%W%i2c4i2c4-xfer QQQ&W&i2c5i2c5-xfer QQQ'W'i2s0i2s0-bus`QQQQQQQHWHsdmmcsdmmc-clkQQ W sdmmc-cmdRQ W sdmmc-cdRQWsdmmc-bus1Rsdmmc-bus4@RRRRQWsdmmc-pwr QQ]W]sdio0sdio0-bus1Rsdio0-bus4@RRRRsdio0-cmdRsdio0-clkQsdio0-cdRsdio0-wpRsdio0-pwrRsdio0-bkpwrRsdio0-intRsdio1sdio1-bus1Rsdio1-bus4@RRRRsdio1-cdRsdio1-wpRsdio1-bkpwrRsdio1-intRsdio1-cmdRsdio1-clkQsdio1-pwr Remmcemmc-clkQQWemmc-cmdRQWemmc-pwr Remmc-bus1Remmc-bus4@RRRRemmc-bus8RRRRRRRRQWemmc-reset QQUWUspi0spi0-clk RQWspi0-cs0 RQWspi0-txRQWspi0-rxRQWspi0-cs1Rspi1spi1-clk RQWspi1-cs0 RQWspi1-rxRQWspi1-txRQWspi2spi2-cs1Rspi2-clkRQ W spi2-cs0RQ#W#spi2-rxRQ"W"spi2-tx RQ!W!uart0uart0-xfer RQQ(W(uart0-ctsRuart0-rtsQuart1uart1-xfer R QQ)W)uart1-cts Ruart1-rts Quart2uart2-xfer RQQ*W*uart3uart3-xfer RQQ+W+uart3-cts Ruart3-rts Quart4uart4-xfer  R QQ,W,uart4-ctsRuart4-rtsQtsadcotp-gpio QQ1W1otp-out QQ2W2pwm0pwm0-pinQQBWBpwm1pwm1-pinQQCWCpwm2pwm2-pinQQDWDpwm3pwm3-pinQQEWEgmacrgmii-pinsQQQQSSSSQQQ SSQQQ6W6rmii-pinsQQQQQQQQQQphy-rstTQ7W7spdifspdif-tx QQGWGpcfg-output-high1QTWTirir-intRQXWXpmicpmic-intRQ@W@usbhost-vbus-drvQQ[W[emmc-pwrseqmmc-pwrseq-emmc^UPdefault =V QWexternal-gmac-clock fixed-clocksY@ ext_gmacQ4W4vsys-regulatorregulator-fixedvcc_sys*LK@BLK@ZQ=W=ir-receivergpio-ir-receiver CWPdefault^Xsoundsimple-audio-cardISPDIFsimple-audio-card,dai-link@1cpu`Ycodec`Zspdif-outlinux,spdif-ditQZWZvcc-host-regulatorregulator-fixedj  ?Pdefault^[Z vcc_hostsdmmc-regulatorregulator-fixed  \ Pdefault^]vcc_sd*2ZB2ZQW #address-cells#size-cellscompatibleinterrupt-parentmodelstdout-pathethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2device_typereginterruptsinterrupt-affinityenable-methodrockchip,pmuresetsoperating-points#cooling-cellsclock-latencyclockscpu0-supplylinux,phandleranges#dma-cellsclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredportsclock-freq-min-maxfifo-depthbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wpnum-slotspinctrl-namespinctrl-0vmmc-supplyvqmmc-supplynon-removablemmc-pwrseq#io-channel-cellsdmasdma-namesreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfassigned-clocksassigned-clock-parentsclock_in_outphy-modephy-supplysnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usrx_delaytx_delayphysphy-namesdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmasystem-power-controllerinl1-supplyinl2-supplyinl3-supplyvp1-supplyvp2-supplyvp3-supplyvp4-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onfcs,suspend-voltage-selectorregulator-boot-onregulator-enable-ramp-delayregulator-ramp-delayvin-supply#pwm-cells#power-domain-cells#reset-cellsassigned-clock-rates#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channelspower-domainsiommusremote-endpoint#iommu-cellsddc-i2c-businterrupt-controller#interrupt-cells#phy-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highreset-gpiossimple-audio-card,namesound-daienable-active-high