[8V(Vt(,chipspark,rayeager-px2rockchip,rk3066a 7Rayeager PX2chosenaliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/dwmmc@1021c000f/dwmmc@10214000l/dwmmc@10218000r/serial@10124000z/serial@10126000/serial@20064000/serial@20068000/spi@20070000/spi@20074000memorymemory`@amba ,arm,amba-busdma-controller@20018000,arm,pl330arm,primecell @ apb_pclk@@dma-controller@2001c000,arm,pl330arm,primecell @ apb_pclk disableddma-controller@20078000,arm,pl330arm,primecell @ apb_pclk44oscillator ,fixed-clockn6xin24ml2-cache-controller@10138000,arm,pl310-cache!/==scu@1013c000,arm,cortex-a9-scuglobal-timer@1013c200,arm,cortex-a9-global-timer   local-timer@1013c600,arm,cortex-a9-twd-timer   interrupt-controller@1013d000,arm,cortex-a9-gic;Pserial@10124000,snps,dw-apb-uart@ "akbaudclkapb_pclk@Lokayxdefault serial@10126000,snps,dw-apb-uart` #akbaudclkapb_pclkAM disabledxdefaultusb@10180000,rockchip,rk3066-usbsnps,dwc2 otgotg@@  usb2-phyokayusb@101c0000 ,snps,dwc2 otghost usb2-phyokayxdefault ethernet@10204000,rockchip,rk3066-emac @<  D hclkmacrefdrmiiokayxdefault  ethernet-phy@0dwmmc@10214000,rockchip,rk2928-dw-mshc!@ Hbiuciuokayxdefault%0:FXdwmmc@10218000,rockchip,rk2928-dw-mshc! Ibiuciuokayxdefault i%s0:dwmmc@1021c000,rockchip,rk2928-dw-mshc! JbiuciuokayiF%s0xdefault :pmu@20004000,rockchip,rk3066-pmusyscon @grf@20008000,syscon   i2c@2002d000,rockchip,rk3066-i2c  ( i2cPokayxdefaultak8963@0d,asahi-kasei,ak8975 xdefault mma8452@1d ,fsl,mma8452xdefault!i2c@2002f000,rockchip,rk3066-i2c  ) Qi2cokayxdefault"tps@2d-#xdefault$%&&&&''&& ,ti,tps65910regulatorsregulator@0vcc_rtcvrtcregulator@1vcc_io'2Z?2Zvio''regulator@2vdd_arm' '?`Wvdd1>>regulator@3vcc_ddr' '?`Wvdd2regulator@5vcc18'w@?w@vdig1regulator@6vdd_11'?vdig2regulator@7vcc_25'&%?&%vpll33regulator@8 vccio_wl'w@?w@vdacregulator@9 vcc25_hdmi'&%?&% vaux1regulator@10vcca_33'2Z?2Z vaux2regulator@11 vcc_rmii'2Z?2Z vaux33regulator@12 vcc28_cif'*?* vmmcregulator@4vdd3regulator@13 vbbpwm@20030000,rockchip,rk2928-pwm iF disabledxdefault(pwm@20030010,rockchip,rk2928-pwm iFokayxdefault)watchdog@2004c000 ,rockchip,rk3066-wdtsnps,dw-wdt K 3okaypwm@20050020,rockchip,rk2928-pwm  iGokayxdefault*pwm@20050030,rockchip,rk2928-pwm 0iG disabledxdefault+i2c@20056000,rockchip,rk3066-i2c ` * Ri2cokayxdefault,i2c@2005a000,rockchip,rk3066-i2c  + Si2cokayxdefault-i2c@2005e000,rockchip,rk3066-i2c  4 Ti2cokayxdefault.serial@20064000,snps,dw-apb-uart @ $akbaudclkapb_pclkBNokayxdefault/serial@20068000,snps,dw-apb-uart  %akbaudclkapb_pclkCOokayxdefault 012saradc@2006c000,rockchip,saradc  tGJsaradcapb_pclkokay3spi@20070000,rockchip,rk3066-spiEHspiclkapb_pclk & 4 4 txrxokayxdefault5678spi@20074000,rockchip,rk3066-spiFIspiclkapb_pclk ' @4 4 txrx disabledxdefault9:;<cpusrockchip,rk3066-smpcpu@0cpu,arm,cortex-a9=(ag8 s 'B@@>cpu@1cpu,arm,cortex-a9=sram@10080000 ,mmio-sram smp-sram@0,rockchip,rk3066-smp-sramPi2s@10118000,rockchip,rk3066-i2s  xdefault?@@txrxi2s_hclki2s_clkK disabledi2s@1011a000,rockchip,rk3066-i2s  xdefaultA@@txrxi2s_hclki2s_clkL disabledi2s@1011c000,rockchip,rk3066-i2s  xdefaultB@ @ txrxi2s_hclki2s_clkM disabledclock-controller@20000000,rockchip,rk3066a-cru   timer@2000e000,snps,dw-apb-timer-osc  .VD timerpclkefuse@20010000,rockchip,rockchip-efuse @[ pclk_efusecpu_leakagetimer@20038000,snps,dw-apb-timer-osc  ,TB timerpclktimer@2003a000,snps,dw-apb-timer-osc  -UC timerpclkphy1,rockchip,rk3066a-usb-phyrockchip,rk3288-usb-phy okayusb-phy0-|Qphyclkusb-phy1-Rphyclkpinctrl,rockchip,rk3066a-pinctrl gpio0@20034000,rockchip,gpio-bank @ 6U8H;PLLgpio1@2003c000,rockchip,gpio-bank  7V8H;Pgpio2@2003e000,rockchip,gpio-bank  8W8H;Pgpio3@20080000,rockchip,gpio-bank  9X8H;PJJgpio4@20084000,rockchip,gpio-bank @ :Y8H;Pgpio6@2000a000,rockchip,gpio-bank  <Z8H;P##pcfg_pull_defaultTEEpcfg_pull_nonejCCemacemac-xferwCCCCCCCC  emac-mdio wCC  rmii-rstwDemmcemmc-clkwEemmc-cmdw Eemmc-rstw Ei2c0i2c0-xfer wCCi2c1i2c1-xfer wCC""i2c2i2c2-xfer wCC,,i2c3i2c3-xfer wCC--i2c4i2c4-xfer wCC..pwm0pwm0-outwC((pwm1pwm1-outwC))pwm2pwm2-outwC**pwm3pwm3-outwC++spi0spi0-clkwE55spi0-cs0wE88spi0-txwE66spi0-rxwE77spi0-cs1wEspi1spi1-clkwE99spi1-cs0wE<<spi1-rxwE;;spi1-txwE::spi1-cs1wEuart0uart0-xfer wEEuart0-ctswEuart0-rtswEuart1uart1-xfer wEEuart1-ctswEuart1-rtswEuart2uart2-xfer wE E//uart3uart3-xfer wEE00uart3-ctswE11uart3-rtswE22sd0sd0-clkwEsd0-cmdw Esd0-cdwEsd0-wpwEsd0-bus-width1w Esd0-bus-width4@w E E E Esd1sd1-clkwEsd1-cmdwEsd1-cdwEsd1-wpwEsd1-bus-width1wEsd1-bus-width4@wEEEEi2s0i2s0-buswEE E E E E EEE??i2s1i2s1-bus`wEEEEEEAAi2s2i2s2-bus`wEEEEEEBBpcfg-output-highDDak8963comp-intwE  irir-intwEFFkeyspwr-keywEGGmma8452gsensor-intwE!!mmcsdmmc-pwrwEKKusb_hosthost-drvwEMMhub-rstwD  sata-pwrwEHHsata-resetw D  usb_otgotg-drvwENNtpspmic-intwE$$pwr-holdwD%%ir-receiver,gpio-ir-receiver #xdefaultFgpio-keys ,gpio-keysbutton@0 # GPIO PowertxdefaultGvsys-regulator,regulator-fixedvsys'LK@?LK@W&&5v-stdby-regulator,regulator-fixed 5v_stdby'LK@?LK@WIIemmc-regulator,regulator-fixed emmc_vccq'-?-&sata-regulator,regulator-fixed xdefaultHusb_5v'LK@?LK@Isdmmc-regulator,regulator-fixed JxdefaultKvcc_sd'2Z?2Z'usb-host-regulator,regulator-fixed LxdefaultM host-pwr'LK@?LK@Iusb-otg-regulator,regulator-fixed LxdefaultNvcc_otg'LK@?LK@I #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4mshc0mshc1mshc2serial0serial1serial2serial3spi0spi1device_typeregrangesinterrupts#dma-cellsclocksclock-nameslinux,phandlestatusclock-frequency#clock-cellsclock-output-namescache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthpinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmaphysphy-namesrockchip,grfmax-speedphy-modephyphy-supplyfifo-depthbus-widthdisable-wpnum-slotsvmmc-supplycap-mmc-highspeedcap-sd-highspeedbroken-cdnon-removablevqmmc-supplyvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-nameregulator-always-onregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-boot-on#pwm-cells#io-channel-cellsvref-supplydmasdma-namesenable-methodnext-level-cacheoperating-pointsclock-latencycpu0-supplyrockchip,playback-channelsrockchip,capture-channels#reset-cells#phy-cellsgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinsoutput-highgpiosgpio-key,wakeuplabellinux,codevin-supplyenable-active-highgpiostartup-delay-us