O#8J(JTCompuLab SBC-iMX71!compulab,sbc-imx7compulab,cl-som-imx7fsl,imx7dchosenaliases%,/soc/aips-bus@30000000/gpio@30200000%2/soc/aips-bus@30000000/gpio@30210000%8/soc/aips-bus@30000000/gpio@30220000%>/soc/aips-bus@30000000/gpio@30230000%D/soc/aips-bus@30000000/gpio@30240000%J/soc/aips-bus@30000000/gpio@30250000%P/soc/aips-bus@30000000/gpio@30260000$V/soc/aips-bus@30800000/i2c@30a20000$[/soc/aips-bus@30800000/i2c@30a30000$`/soc/aips-bus@30800000/i2c@30a40000$e/soc/aips-bus@30800000/i2c@30a50000&j/soc/aips-bus@30800000/usdhc@30b40000&o/soc/aips-bus@30800000/usdhc@30b50000&t/soc/aips-bus@30800000/usdhc@30b60000'y/soc/aips-bus@30800000/serial@30860000'/soc/aips-bus@30800000/serial@30890000'/soc/aips-bus@30800000/serial@30880000'/soc/aips-bus@30800000/serial@30a60000'/soc/aips-bus@30800000/serial@30a70000'/soc/aips-bus@30800000/serial@30a80000'/soc/aips-bus@30800000/serial@30a90000memorymemorycpuscpu@0!arm,cortex-a7cpu2g8 lcpu@1!arm,cortex-a7cpuinterrupt-controller@31001000!arm,cortex-a7-gic 11 1@ 1` clock-cki !fixed-clock&3Cckilclock-osc !fixed-clock&3n6Coscetr@30086000 !arm,coresight-tmcarm,primecell0`J Vapb_pclkportendpointbmtpiu@30087000!!arm,coresight-tpiuarm,primecell0pJ Vapb_pclkportendpointbmreplicator!arm,coresight-replicatorportsport@0endpointmport@1endpointmport@2endpointbmetf@30084000 !arm,coresight-tmcarm,primecell0@J Vapb_pclkportsport@0endpointbm  port@1endpointmfunnel@30083000#!arm,coresight-funnelarm,primecell00J Vapb_pclkportsport@0endpointbm   port@1endpointbport@2endpointm funnel@30041000#!arm,coresight-funnelarm,primecell0J Vapb_pclkportsport@0endpointbm port@1endpointbm port@2endpointm   etm@3007c000"!arm,coresight-etm3xarm,primecell0}J Vapb_pclkportendpointm  etm@3007d000"!arm,coresight-etm3xarm,primecell0 V}J Vapb_pclkportendpointm  soc !simple-busaips-bus@30000000!fsl,aips-bussimple-bus0@gpio@30200000!fsl,imx7d-gpiofsl,imx35-gpio0 @A((gpio@30210000!fsl,imx7d-gpiofsl,imx35-gpio0!BCgpio@30220000!fsl,imx7d-gpiofsl,imx35-gpio0"DEgpio@30230000!fsl,imx7d-gpiofsl,imx35-gpio0#FGgpio@30240000!fsl,imx7d-gpiofsl,imx35-gpio0$HI""gpio@30250000!fsl,imx7d-gpiofsl,imx35-gpio0%JKgpio@30260000!fsl,imx7d-gpiofsl,imx35-gpio0&LMwdog@30280000!fsl,imx7d-wdtfsl,imx21-wdt0( NBwdog@30290000!fsl,imx7d-wdtfsl,imx21-wdt0) O disabledwdog@302a0000!fsl,imx7d-wdtfsl,imx21-wdt0*   disabledwdog@302b0000!fsl,imx7d-wdtfsl,imx21-wdt0+ m disablediomuxc-lpsr@302c0000!fsl,imx7d-iomuxc-lpsr0,gpt@302d0000!fsl,imx7d-gptfsl,imx6sx-gpt0- 7.Vipgpergpt@302e0000!fsl,imx7d-gptfsl,imx6sx-gpt0. 62Vipgper disabledgpt@302f0000!fsl,imx7d-gptfsl,imx6sx-gpt0/ 56Vipgper disabledgpt@30300000!fsl,imx7d-gptfsl,imx6sx-gpt00 4:Vipgper disablediomuxc@30330000!fsl,imx7d-iomuxc03enet1grpPh XDHLPT@,048<$$enet2grp  xtx|&&i2c2grp0T@P@uart1grp0,y(yusbotg1grpDusdhc3grpDY@HYLYPYTYXY\Y`YdYh##usdhc1grpY YYYYYY!!iomuxc-gpr@30340000!fsl,imx7d-iomuxc-gprsyscon04ocotp-ctrl@30350000!syscon05 disabledanatop@303600004!fsl,imx7d-anatopfsl,imx6q-anatopsysconsimple-bus0613regulator-vdd1p0d@210!fsl,anatop-regulatorvdd1p0d 5O4F[p 5Osnvs@30370000#!fsl,sec-v4.0-monsysconsimple-mfd07snvs-rtc-lp!fsl,sec-v4.0-mon-rtc-lp?4snvs-poweroff!syscon-poweroff?8`snvs-powerkey!fsl,sec-v4.0-pwrkey tccm@30380000!fsl,imx7d-ccm08UV& Vckiloscsrc@30390000#!fsl,imx7d-srcfsl,imx51-srcsyscon09 Yaips-bus@30400000!fsl,aips-bussimple-bus0@@adc@30610000!fsl,imx7d-adc0a bVadc disabledadc@30620000!fsl,imx7d-adc0b cVadc disabledpwm@30660000!fsl,imx7d-pwmfsl,imx27-pwm0f QVipgper disabledpwm@30670000!fsl,imx7d-pwmfsl,imx27-pwm0g RVipgper disabledpwm@30680000!fsl,imx7d-pwmfsl,imx27-pwm0h SVipgper disabledpwm@30690000!fsl,imx7d-pwmfsl,imx27-pwm0i TVipgper disabledaips-bus@30800000!fsl,aips-bussimple-bus0@serial@30860000!fsl,imx7d-uartfsl,imx6q-uart0 Vipgperokaydefault # serial@30890000!fsl,imx7d-uartfsl,imx6q-uart0 Vipgper disabledserial@30880000!fsl,imx7d-uartfsl,imx6q-uart0 Vipgper disabledi2c@30a20000!fsl,imx7d-i2cfsl,imx21-i2c0 # disabledi2c@30a30000!fsl,imx7d-i2cfsl,imx21-i2c0 $okaydefault pmic@8!fsl,pfuze3000regulatorssw1a `:L`jsw1b `:L`jsw2`::Lsw3 -P:LswbstLK@N0vsnvsB@-:Lvrefddr:Lvldo1w@2ZLvldo2 5vccsd+|2ZLv33+|2ZLvldo3w@2ZLvldo4w@2ZLpca9555@20 !nxp,pca9555 eeprom@50 !atmel,24c08Pui2c@30a40000!fsl,imx7d-i2cfsl,imx21-i2c0 % disabledi2c@30a50000!fsl,imx7d-i2cfsl,imx21-i2c0 & disabledserial@30a60000!fsl,imx7d-uartfsl,imx6q-uart0 Vipgper disabledserial@30a70000!fsl,imx7d-uartfsl,imx6q-uart0 Vipgper disabledserial@30a80000!fsl,imx7d-uartfsl,imx6q-uart0 Vipgper disabledserial@30a90000!fsl,imx7d-uartfsl,imx6q-uart0 ~Vipgper disabledusb@30b10000!fsl,imx7d-usbfsl,imx27-usb0 +~okaydefault usb@30b20000!fsl,imx7d-usbfsl,imx27-usb0 *~ disabledusb@30b30000!fsl,imx7d-usbfsl,imx27-usb0 (~ hsichost disabledusbmisc@30b10200$!fsl,imx7d-usbmiscfsl,imx6q-usbmisc0usbmisc@30b20200$!fsl,imx7d-usbmiscfsl,imx6q-usbmisc0usbmisc@30b30200$!fsl,imx7d-usbmiscfsl,imx6q-usbmisc0  usbphynop1!usb-nop-xceiv Vmain_clkusbphynop2!usb-nop-xceiv Vmain_clkusbphynop3!usb-nop-xceivn Vmain_clkusdhc@30b40000!!fsl,imx7d-usdhcfsl,imx6sl-usdhc0  Vipgahbperokaydefault ! " "usdhc@30b50000!!fsl,imx7d-usdhcfsl,imx6sl-usdhc0  Vipgahbper disabledusdhc@30b60000!!fsl,imx7d-usdhcfsl,imx6sl-usdhc0  Vipgahbperokaydefault #ׄ(ethernet@30be0000!fsl,imx7d-fecfsl,imx6sx-fec0$vwx(RR*"Vipgahbptpenet_clk_refenet_out6Hokaydefault $#+Zrgmiic%nmdioethernet-phy@0%%ethernet-phy@1''ethernet@30bf0000!fsl,imx7d-fecfsl,imx6sx-fec0$def(RR*"Vipgahbptpenet_clk_refenet_out6Hokaydefault &#+Zrgmiic'nregulator-vbus!regulator-fixedusb_otg1_vbusLK@LK@ ( #address-cells#size-cellsmodelcompatiblegpio0gpio1gpio2gpio3gpio4gpio5gpio6i2c0i2c1i2c2i2c3mmc0mmc1mmc2serial0serial1serial2serial3serial4serial5serial6device_typeregoperating-pointsclock-latencyclocksarm-supplylinux,phandle#interrupt-cellsinterrupt-controller#clock-cellsclock-frequencyclock-output-namesclock-namesslave-moderemote-endpointcpuarm,primecell-periphidinterrupt-parentrangesinterruptsgpio-controller#gpio-cellsstatusfsl,input-selfsl,pinsregulator-nameregulator-min-microvoltregulator-max-microvoltanatop-reg-offsetanatop-vol-bit-shiftanatop-vol-bit-widthanatop-min-bit-valanatop-min-voltageanatop-max-voltageanatop-enable-bitregmapmasklinux,keycodewakeup-source#reset-cells#pwm-cellspinctrl-namespinctrl-0assigned-clocksassigned-clock-parentsregulator-boot-onregulator-always-onregulator-ramp-delaypagesizefsl,usbphyfsl,usbmiscphy-clkgate-delay-usvbus-supplyphy_typedr_mode#index-cellsbus-widthcd-gpioswp-gpiosenable-sdio-wakeupassigned-clock-ratesfsl,tuning-stepnon-removablefsl,num-tx-queuesfsl,num-rx-queuesphy-modephy-handlefsl,magic-packetgpioenable-active-high