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#
#Copyright (c) 2023 Intel Corporation
#
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#  you may not use this file except in compliance with the License.
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########################################################################
## file: xed-reg-tables-gpr.txt
########################################################################


#######################################################################
# Expand the generic registers using the effective address size EASZ
#######################################################################
xed_reg_enum_t ArAX()::
EASZ=1 | OUTREG=XED_REG_AX
EASZ=2 | OUTREG=XED_REG_EAX
EASZ=3 | OUTREG=XED_REG_RAX
xed_reg_enum_t ArBX()::
EASZ=1 | OUTREG=XED_REG_BX
EASZ=2 | OUTREG=XED_REG_EBX
EASZ=3 | OUTREG=XED_REG_RBX
xed_reg_enum_t ArCX()::
EASZ=1 | OUTREG=XED_REG_CX
EASZ=2 | OUTREG=XED_REG_ECX
EASZ=3 | OUTREG=XED_REG_RCX
xed_reg_enum_t ArDX()::
EASZ=1 | OUTREG=XED_REG_DX
EASZ=2 | OUTREG=XED_REG_EDX
EASZ=3 | OUTREG=XED_REG_RDX

xed_reg_enum_t ArSI()::
EASZ=1 | OUTREG=XED_REG_SI
EASZ=2 | OUTREG=XED_REG_ESI
EASZ=3 | OUTREG=XED_REG_RSI
xed_reg_enum_t ArDI()::
EASZ=1 | OUTREG=XED_REG_DI
EASZ=2 | OUTREG=XED_REG_EDI
EASZ=3 | OUTREG=XED_REG_RDI
xed_reg_enum_t ArSP()::
EASZ=1 | OUTREG=XED_REG_SP
EASZ=2 | OUTREG=XED_REG_ESP
EASZ=3 | OUTREG=XED_REG_RSP
xed_reg_enum_t ArBP()::
EASZ=1 | OUTREG=XED_REG_BP
EASZ=2 | OUTREG=XED_REG_EBP
EASZ=3 | OUTREG=XED_REG_RBP

xed_reg_enum_t SrSP()::
smode16 | OUTREG=XED_REG_SP
smode32 | OUTREG=XED_REG_ESP
smode64 | OUTREG=XED_REG_RSP
xed_reg_enum_t SrBP()::
smode16 | OUTREG=XED_REG_BP
smode32 | OUTREG=XED_REG_EBP
smode64 | OUTREG=XED_REG_RBP

xed_reg_enum_t Ar8()::
EASZ=1 | OUTREG=XED_REG_R8W
EASZ=2 | OUTREG=XED_REG_R8D
EASZ=3 | OUTREG=XED_REG_R8
xed_reg_enum_t Ar9()::
EASZ=1 | OUTREG=XED_REG_R9W
EASZ=2 | OUTREG=XED_REG_R9D
EASZ=3 | OUTREG=XED_REG_R9
xed_reg_enum_t Ar10()::
EASZ=1 | OUTREG=XED_REG_R10W
EASZ=2 | OUTREG=XED_REG_R10D
EASZ=3 | OUTREG=XED_REG_R10
xed_reg_enum_t Ar11()::
EASZ=1 | OUTREG=XED_REG_R11W
EASZ=2 | OUTREG=XED_REG_R11D
EASZ=3 | OUTREG=XED_REG_R11
xed_reg_enum_t Ar12()::
EASZ=1 | OUTREG=XED_REG_R12W
EASZ=2 | OUTREG=XED_REG_R12D
EASZ=3 | OUTREG=XED_REG_R12
xed_reg_enum_t Ar13()::
EASZ=1 | OUTREG=XED_REG_R13W
EASZ=2 | OUTREG=XED_REG_R13D
EASZ=3 | OUTREG=XED_REG_R13
xed_reg_enum_t Ar14()::
EASZ=1 | OUTREG=XED_REG_R14W
EASZ=2 | OUTREG=XED_REG_R14D
EASZ=3 | OUTREG=XED_REG_R14
xed_reg_enum_t Ar15()::
EASZ=1 | OUTREG=XED_REG_R15W
EASZ=2 | OUTREG=XED_REG_R15D
EASZ=3 | OUTREG=XED_REG_R15

# EGPRs
xed_reg_enum_t Ar16()::
EASZ=1 | OUTREG=XED_REG_R16W HAS_EGPR=1
EASZ=2 | OUTREG=XED_REG_R16D HAS_EGPR=1
EASZ=3 | OUTREG=XED_REG_R16  HAS_EGPR=1
xed_reg_enum_t Ar17()::
EASZ=1 | OUTREG=XED_REG_R17W HAS_EGPR=1
EASZ=2 | OUTREG=XED_REG_R17D HAS_EGPR=1
EASZ=3 | OUTREG=XED_REG_R17  HAS_EGPR=1
xed_reg_enum_t Ar18()::
EASZ=1 | OUTREG=XED_REG_R18W HAS_EGPR=1
EASZ=2 | OUTREG=XED_REG_R18D HAS_EGPR=1
EASZ=3 | OUTREG=XED_REG_R18  HAS_EGPR=1
xed_reg_enum_t Ar19()::
EASZ=1 | OUTREG=XED_REG_R19W HAS_EGPR=1
EASZ=2 | OUTREG=XED_REG_R19D HAS_EGPR=1
EASZ=3 | OUTREG=XED_REG_R19  HAS_EGPR=1
xed_reg_enum_t Ar20()::
EASZ=1 | OUTREG=XED_REG_R20W HAS_EGPR=1
EASZ=2 | OUTREG=XED_REG_R20D HAS_EGPR=1
EASZ=3 | OUTREG=XED_REG_R20  HAS_EGPR=1
xed_reg_enum_t Ar21()::
EASZ=1 | OUTREG=XED_REG_R21W HAS_EGPR=1
EASZ=2 | OUTREG=XED_REG_R21D HAS_EGPR=1
EASZ=3 | OUTREG=XED_REG_R21  HAS_EGPR=1
xed_reg_enum_t Ar22()::
EASZ=1 | OUTREG=XED_REG_R22W HAS_EGPR=1
EASZ=2 | OUTREG=XED_REG_R22D HAS_EGPR=1
EASZ=3 | OUTREG=XED_REG_R22  HAS_EGPR=1
xed_reg_enum_t Ar23()::
EASZ=1 | OUTREG=XED_REG_R23W HAS_EGPR=1
EASZ=2 | OUTREG=XED_REG_R23D HAS_EGPR=1
EASZ=3 | OUTREG=XED_REG_R23  HAS_EGPR=1
xed_reg_enum_t Ar24()::
EASZ=1 | OUTREG=XED_REG_R24W HAS_EGPR=1
EASZ=2 | OUTREG=XED_REG_R24D HAS_EGPR=1
EASZ=3 | OUTREG=XED_REG_R24  HAS_EGPR=1
xed_reg_enum_t Ar25()::
EASZ=1 | OUTREG=XED_REG_R25W HAS_EGPR=1
EASZ=2 | OUTREG=XED_REG_R25D HAS_EGPR=1
EASZ=3 | OUTREG=XED_REG_R25  HAS_EGPR=1
xed_reg_enum_t Ar26()::
EASZ=1 | OUTREG=XED_REG_R26W HAS_EGPR=1
EASZ=2 | OUTREG=XED_REG_R26D HAS_EGPR=1
EASZ=3 | OUTREG=XED_REG_R26  HAS_EGPR=1
xed_reg_enum_t Ar27()::
EASZ=1 | OUTREG=XED_REG_R27W HAS_EGPR=1
EASZ=2 | OUTREG=XED_REG_R27D HAS_EGPR=1
EASZ=3 | OUTREG=XED_REG_R27  HAS_EGPR=1
xed_reg_enum_t Ar28()::
EASZ=1 | OUTREG=XED_REG_R28W HAS_EGPR=1
EASZ=2 | OUTREG=XED_REG_R28D HAS_EGPR=1
EASZ=3 | OUTREG=XED_REG_R28  HAS_EGPR=1
xed_reg_enum_t Ar29()::
EASZ=1 | OUTREG=XED_REG_R29W HAS_EGPR=1
EASZ=2 | OUTREG=XED_REG_R29D HAS_EGPR=1
EASZ=3 | OUTREG=XED_REG_R29  HAS_EGPR=1
xed_reg_enum_t Ar30()::
EASZ=1 | OUTREG=XED_REG_R30W HAS_EGPR=1
EASZ=2 | OUTREG=XED_REG_R30D HAS_EGPR=1
EASZ=3 | OUTREG=XED_REG_R30  HAS_EGPR=1
xed_reg_enum_t Ar31()::
EASZ=1 | OUTREG=XED_REG_R31W HAS_EGPR=1
EASZ=2 | OUTREG=XED_REG_R31D HAS_EGPR=1
EASZ=3 | OUTREG=XED_REG_R31  HAS_EGPR=1

xed_reg_enum_t rIP()::
mode16 | OUTREG=XED_REG_EIP
mode32 | OUTREG=XED_REG_EIP
mode64 | OUTREG=XED_REG_RIP

xed_reg_enum_t rIPa()::
EASZ=2 | OUTREG=XED_REG_EIP
EASZ=3 | OUTREG=XED_REG_RIP

#######################################################################
# Expand the generic registers using the effective address size EOSZ - limit 32b
#######################################################################


xed_reg_enum_t OeAX()::
EOSZ=1 | OUTREG=XED_REG_AX
EOSZ=2 | OUTREG=XED_REG_EAX
EOSZ=3 | OUTREG=XED_REG_EAX


#######################################################################
# Expand the generic registers using the effective address size EOSZ - limit 64b
#######################################################################

xed_reg_enum_t OrAX()::
EOSZ=1 | OUTREG=XED_REG_AX
EOSZ=2 | OUTREG=XED_REG_EAX
EOSZ=3 | OUTREG=XED_REG_RAX
xed_reg_enum_t OrDX()::
EOSZ=1 | OUTREG=XED_REG_DX
EOSZ=2 | OUTREG=XED_REG_EDX
EOSZ=3 | OUTREG=XED_REG_RDX

# only used for VIA PADLOCK ISA:
xed_reg_enum_t OrCX()::
EOSZ=1 | OUTREG=XED_REG_CX
EOSZ=2 | OUTREG=XED_REG_ECX
EOSZ=3 | OUTREG=XED_REG_RCX
# only used for VIA PADLOCK ISA:
xed_reg_enum_t OrBX()::
EOSZ=1 | OUTREG=XED_REG_BX
EOSZ=2 | OUTREG=XED_REG_EBX
EOSZ=3 | OUTREG=XED_REG_RBX

xed_reg_enum_t OrSP()::
EOSZ=1 | OUTREG=XED_REG_SP
EOSZ=2 | OUTREG=XED_REG_ESP
EOSZ=3 | OUTREG=XED_REG_RSP
xed_reg_enum_t OrBP()::
EOSZ=1 | OUTREG=XED_REG_BP
EOSZ=2 | OUTREG=XED_REG_EBP
EOSZ=3 | OUTREG=XED_REG_RBP


#####################################################


# Things that scale with effective operand size 



# When used as the MODRM.REG register
xed_reg_enum_t GPRv_R()::
EOSZ=3 | OUTREG=GPR64_R() 
EOSZ=2 | OUTREG=GPR32_R() 
EOSZ=1 | OUTREG=GPR16_R() 

xed_reg_enum_t GPRv_SB()::
EOSZ=3 | OUTREG=GPR64_SB() 
EOSZ=2 | OUTREG=GPR32_SB() 
EOSZ=1 | OUTREG=GPR16_SB() 

xed_reg_enum_t GPRz_R()::
EOSZ=3 | OUTREG=GPR32_R() 
EOSZ=2 | OUTREG=GPR32_R() 
EOSZ=1 | OUTREG=GPR16_R() 

xed_reg_enum_t GPRy_R()::
EOSZ=3 | OUTREG=GPR64_R() 
EOSZ=2 | OUTREG=GPR32_R() 
EOSZ=1 | OUTREG=GPR32_R() 

# When used as the MOD=11/RM register
xed_reg_enum_t GPRv_B()::
EOSZ=3 | OUTREG=GPR64_B() 
EOSZ=2 | OUTREG=GPR32_B() 
EOSZ=1 | OUTREG=GPR16_B() 

xed_reg_enum_t GPRz_B()::
EOSZ=3 | OUTREG=GPR32_B() 
EOSZ=2 | OUTREG=GPR32_B() 
EOSZ=1 | OUTREG=GPR16_B() 

xed_reg_enum_t GPRy_B()::
EOSZ=3 | OUTREG=GPR64_B() 
EOSZ=2 | OUTREG=GPR32_B() 
EOSZ=1 | OUTREG=GPR32_B() 


#####################################

xed_reg_enum_t GPR64_R()::
REXR4=0 REXR=0 REG=0x0  | OUTREG=XED_REG_RAX
REXR4=0 REXR=0 REG=0x1  | OUTREG=XED_REG_RCX
REXR4=0 REXR=0 REG=0x2  | OUTREG=XED_REG_RDX
REXR4=0 REXR=0 REG=0x3  | OUTREG=XED_REG_RBX
REXR4=0 REXR=0 REG=0x4  | OUTREG=XED_REG_RSP
REXR4=0 REXR=0 REG=0x5  | OUTREG=XED_REG_RBP
REXR4=0 REXR=0 REG=0x6  | OUTREG=XED_REG_RSI
REXR4=0 REXR=0 REG=0x7  | OUTREG=XED_REG_RDI
REXR4=0 REXR=1 REG=0x0  | OUTREG=XED_REG_R8
REXR4=0 REXR=1 REG=0x1  | OUTREG=XED_REG_R9
REXR4=0 REXR=1 REG=0x2  | OUTREG=XED_REG_R10
REXR4=0 REXR=1 REG=0x3  | OUTREG=XED_REG_R11
REXR4=0 REXR=1 REG=0x4  | OUTREG=XED_REG_R12
REXR4=0 REXR=1 REG=0x5  | OUTREG=XED_REG_R13
REXR4=0 REXR=1 REG=0x6  | OUTREG=XED_REG_R14
REXR4=0 REXR=1 REG=0x7  | OUTREG=XED_REG_R15
#EGPRs
REXR4=1 REXR=0 REG=0x0  | OUTREG=XED_REG_R16 HAS_EGPR=1
REXR4=1 REXR=0 REG=0x1  | OUTREG=XED_REG_R17 HAS_EGPR=1
REXR4=1 REXR=0 REG=0x2  | OUTREG=XED_REG_R18 HAS_EGPR=1
REXR4=1 REXR=0 REG=0x3  | OUTREG=XED_REG_R19 HAS_EGPR=1
REXR4=1 REXR=0 REG=0x4  | OUTREG=XED_REG_R20 HAS_EGPR=1
REXR4=1 REXR=0 REG=0x5  | OUTREG=XED_REG_R21 HAS_EGPR=1
REXR4=1 REXR=0 REG=0x6  | OUTREG=XED_REG_R22 HAS_EGPR=1
REXR4=1 REXR=0 REG=0x7  | OUTREG=XED_REG_R23 HAS_EGPR=1
REXR4=1 REXR=1 REG=0x0  | OUTREG=XED_REG_R24 HAS_EGPR=1
REXR4=1 REXR=1 REG=0x1  | OUTREG=XED_REG_R25 HAS_EGPR=1
REXR4=1 REXR=1 REG=0x2  | OUTREG=XED_REG_R26 HAS_EGPR=1
REXR4=1 REXR=1 REG=0x3  | OUTREG=XED_REG_R27 HAS_EGPR=1
REXR4=1 REXR=1 REG=0x4  | OUTREG=XED_REG_R28 HAS_EGPR=1
REXR4=1 REXR=1 REG=0x5  | OUTREG=XED_REG_R29 HAS_EGPR=1
REXR4=1 REXR=1 REG=0x6  | OUTREG=XED_REG_R30 HAS_EGPR=1
REXR4=1 REXR=1 REG=0x7  | OUTREG=XED_REG_R31 HAS_EGPR=1


xed_reg_enum_t GPR64_B()::
REXB4=0 REXB=0 RM=0x0  | OUTREG=XED_REG_RAX
REXB4=0 REXB=0 RM=0x1  | OUTREG=XED_REG_RCX
REXB4=0 REXB=0 RM=0x2  | OUTREG=XED_REG_RDX
REXB4=0 REXB=0 RM=0x3  | OUTREG=XED_REG_RBX
REXB4=0 REXB=0 RM=0x4  | OUTREG=XED_REG_RSP
REXB4=0 REXB=0 RM=0x5  | OUTREG=XED_REG_RBP
REXB4=0 REXB=0 RM=0x6  | OUTREG=XED_REG_RSI
REXB4=0 REXB=0 RM=0x7  | OUTREG=XED_REG_RDI
REXB4=0 REXB=1 RM=0x0  | OUTREG=XED_REG_R8
REXB4=0 REXB=1 RM=0x1  | OUTREG=XED_REG_R9
REXB4=0 REXB=1 RM=0x2  | OUTREG=XED_REG_R10
REXB4=0 REXB=1 RM=0x3  | OUTREG=XED_REG_R11
REXB4=0 REXB=1 RM=0x4  | OUTREG=XED_REG_R12
REXB4=0 REXB=1 RM=0x5  | OUTREG=XED_REG_R13
REXB4=0 REXB=1 RM=0x6  | OUTREG=XED_REG_R14
REXB4=0 REXB=1 RM=0x7  | OUTREG=XED_REG_R15
#EGPRs
REXB4=1 REXB=0 RM=0x0  | OUTREG=XED_REG_R16 HAS_EGPR=1
REXB4=1 REXB=0 RM=0x1  | OUTREG=XED_REG_R17 HAS_EGPR=1
REXB4=1 REXB=0 RM=0x2  | OUTREG=XED_REG_R18 HAS_EGPR=1
REXB4=1 REXB=0 RM=0x3  | OUTREG=XED_REG_R19 HAS_EGPR=1
REXB4=1 REXB=0 RM=0x4  | OUTREG=XED_REG_R20 HAS_EGPR=1
REXB4=1 REXB=0 RM=0x5  | OUTREG=XED_REG_R21 HAS_EGPR=1
REXB4=1 REXB=0 RM=0x6  | OUTREG=XED_REG_R22 HAS_EGPR=1
REXB4=1 REXB=0 RM=0x7  | OUTREG=XED_REG_R23 HAS_EGPR=1
REXB4=1 REXB=1 RM=0x0  | OUTREG=XED_REG_R24 HAS_EGPR=1
REXB4=1 REXB=1 RM=0x1  | OUTREG=XED_REG_R25 HAS_EGPR=1
REXB4=1 REXB=1 RM=0x2  | OUTREG=XED_REG_R26 HAS_EGPR=1
REXB4=1 REXB=1 RM=0x3  | OUTREG=XED_REG_R27 HAS_EGPR=1
REXB4=1 REXB=1 RM=0x4  | OUTREG=XED_REG_R28 HAS_EGPR=1
REXB4=1 REXB=1 RM=0x5  | OUTREG=XED_REG_R29 HAS_EGPR=1
REXB4=1 REXB=1 RM=0x6  | OUTREG=XED_REG_R30 HAS_EGPR=1
REXB4=1 REXB=1 RM=0x7  | OUTREG=XED_REG_R31 HAS_EGPR=1

xed_reg_enum_t GPR64_SB()::
REXB4=0 REXB=0 SRM=0x0  | OUTREG=XED_REG_RAX
REXB4=0 REXB=0 SRM=0x1  | OUTREG=XED_REG_RCX
REXB4=0 REXB=0 SRM=0x2  | OUTREG=XED_REG_RDX
REXB4=0 REXB=0 SRM=0x3  | OUTREG=XED_REG_RBX
REXB4=0 REXB=0 SRM=0x4  | OUTREG=XED_REG_RSP
REXB4=0 REXB=0 SRM=0x5  | OUTREG=XED_REG_RBP
REXB4=0 REXB=0 SRM=0x6  | OUTREG=XED_REG_RSI
REXB4=0 REXB=0 SRM=0x7  | OUTREG=XED_REG_RDI
REXB4=0 REXB=1 SRM=0x0  | OUTREG=XED_REG_R8
REXB4=0 REXB=1 SRM=0x1  | OUTREG=XED_REG_R9
REXB4=0 REXB=1 SRM=0x2  | OUTREG=XED_REG_R10
REXB4=0 REXB=1 SRM=0x3  | OUTREG=XED_REG_R11
REXB4=0 REXB=1 SRM=0x4  | OUTREG=XED_REG_R12
REXB4=0 REXB=1 SRM=0x5  | OUTREG=XED_REG_R13
REXB4=0 REXB=1 SRM=0x6  | OUTREG=XED_REG_R14
REXB4=0 REXB=1 SRM=0x7  | OUTREG=XED_REG_R15
#EGPRs
REXB4=1 REXB=0 SRM=0x0  | OUTREG=XED_REG_R16 HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x1  | OUTREG=XED_REG_R17 HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x2  | OUTREG=XED_REG_R18 HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x3  | OUTREG=XED_REG_R19 HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x4  | OUTREG=XED_REG_R20 HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x5  | OUTREG=XED_REG_R21 HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x6  | OUTREG=XED_REG_R22 HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x7  | OUTREG=XED_REG_R23 HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x0  | OUTREG=XED_REG_R24 HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x1  | OUTREG=XED_REG_R25 HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x2  | OUTREG=XED_REG_R26 HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x3  | OUTREG=XED_REG_R27 HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x4  | OUTREG=XED_REG_R28 HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x5  | OUTREG=XED_REG_R29 HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x6  | OUTREG=XED_REG_R30 HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x7  | OUTREG=XED_REG_R31 HAS_EGPR=1

#################################


xed_reg_enum_t GPR32_R()::
REXR4=0 REXR=0 REG=0x0  | OUTREG=XED_REG_EAX
REXR4=0 REXR=0 REG=0x1  | OUTREG=XED_REG_ECX
REXR4=0 REXR=0 REG=0x2  | OUTREG=XED_REG_EDX
REXR4=0 REXR=0 REG=0x3  | OUTREG=XED_REG_EBX
REXR4=0 REXR=0 REG=0x4  | OUTREG=XED_REG_ESP
REXR4=0 REXR=0 REG=0x5  | OUTREG=XED_REG_EBP
REXR4=0 REXR=0 REG=0x6  | OUTREG=XED_REG_ESI
REXR4=0 REXR=0 REG=0x7  | OUTREG=XED_REG_EDI
REXR4=0 REXR=1 REG=0x0  | OUTREG=XED_REG_R8D
REXR4=0 REXR=1 REG=0x1  | OUTREG=XED_REG_R9D
REXR4=0 REXR=1 REG=0x2  | OUTREG=XED_REG_R10D
REXR4=0 REXR=1 REG=0x3  | OUTREG=XED_REG_R11D
REXR4=0 REXR=1 REG=0x4  | OUTREG=XED_REG_R12D
REXR4=0 REXR=1 REG=0x5  | OUTREG=XED_REG_R13D
REXR4=0 REXR=1 REG=0x6  | OUTREG=XED_REG_R14D
REXR4=0 REXR=1 REG=0x7  | OUTREG=XED_REG_R15D
#EGPRs
REXR4=1 REXR=0 REG=0x0  | OUTREG=XED_REG_R16D HAS_EGPR=1
REXR4=1 REXR=0 REG=0x1  | OUTREG=XED_REG_R17D HAS_EGPR=1
REXR4=1 REXR=0 REG=0x2  | OUTREG=XED_REG_R18D HAS_EGPR=1
REXR4=1 REXR=0 REG=0x3  | OUTREG=XED_REG_R19D HAS_EGPR=1
REXR4=1 REXR=0 REG=0x4  | OUTREG=XED_REG_R20D HAS_EGPR=1
REXR4=1 REXR=0 REG=0x5  | OUTREG=XED_REG_R21D HAS_EGPR=1
REXR4=1 REXR=0 REG=0x6  | OUTREG=XED_REG_R22D HAS_EGPR=1
REXR4=1 REXR=0 REG=0x7  | OUTREG=XED_REG_R23D HAS_EGPR=1
REXR4=1 REXR=1 REG=0x0  | OUTREG=XED_REG_R24D HAS_EGPR=1
REXR4=1 REXR=1 REG=0x1  | OUTREG=XED_REG_R25D HAS_EGPR=1
REXR4=1 REXR=1 REG=0x2  | OUTREG=XED_REG_R26D HAS_EGPR=1
REXR4=1 REXR=1 REG=0x3  | OUTREG=XED_REG_R27D HAS_EGPR=1
REXR4=1 REXR=1 REG=0x4  | OUTREG=XED_REG_R28D HAS_EGPR=1
REXR4=1 REXR=1 REG=0x5  | OUTREG=XED_REG_R29D HAS_EGPR=1
REXR4=1 REXR=1 REG=0x6  | OUTREG=XED_REG_R30D HAS_EGPR=1
REXR4=1 REXR=1 REG=0x7  | OUTREG=XED_REG_R31D HAS_EGPR=1

xed_reg_enum_t GPR32_B()::
REXB4=0 REXB=0 RM=0x0  | OUTREG=XED_REG_EAX
REXB4=0 REXB=0 RM=0x1  | OUTREG=XED_REG_ECX
REXB4=0 REXB=0 RM=0x2  | OUTREG=XED_REG_EDX
REXB4=0 REXB=0 RM=0x3  | OUTREG=XED_REG_EBX
REXB4=0 REXB=0 RM=0x4  | OUTREG=XED_REG_ESP
REXB4=0 REXB=0 RM=0x5  | OUTREG=XED_REG_EBP
REXB4=0 REXB=0 RM=0x6  | OUTREG=XED_REG_ESI
REXB4=0 REXB=0 RM=0x7  | OUTREG=XED_REG_EDI
REXB4=0 REXB=1 RM=0x0  | OUTREG=XED_REG_R8D
REXB4=0 REXB=1 RM=0x1  | OUTREG=XED_REG_R9D
REXB4=0 REXB=1 RM=0x2  | OUTREG=XED_REG_R10D
REXB4=0 REXB=1 RM=0x3  | OUTREG=XED_REG_R11D
REXB4=0 REXB=1 RM=0x4  | OUTREG=XED_REG_R12D
REXB4=0 REXB=1 RM=0x5  | OUTREG=XED_REG_R13D
REXB4=0 REXB=1 RM=0x6  | OUTREG=XED_REG_R14D
REXB4=0 REXB=1 RM=0x7  | OUTREG=XED_REG_R15D
#EGPRs
REXB4=1 REXB=0 RM=0x0  | OUTREG=XED_REG_R16D HAS_EGPR=1
REXB4=1 REXB=0 RM=0x1  | OUTREG=XED_REG_R17D HAS_EGPR=1
REXB4=1 REXB=0 RM=0x2  | OUTREG=XED_REG_R18D HAS_EGPR=1
REXB4=1 REXB=0 RM=0x3  | OUTREG=XED_REG_R19D HAS_EGPR=1
REXB4=1 REXB=0 RM=0x4  | OUTREG=XED_REG_R20D HAS_EGPR=1
REXB4=1 REXB=0 RM=0x5  | OUTREG=XED_REG_R21D HAS_EGPR=1
REXB4=1 REXB=0 RM=0x6  | OUTREG=XED_REG_R22D HAS_EGPR=1
REXB4=1 REXB=0 RM=0x7  | OUTREG=XED_REG_R23D HAS_EGPR=1
REXB4=1 REXB=1 RM=0x0  | OUTREG=XED_REG_R24D HAS_EGPR=1
REXB4=1 REXB=1 RM=0x1  | OUTREG=XED_REG_R25D HAS_EGPR=1
REXB4=1 REXB=1 RM=0x2  | OUTREG=XED_REG_R26D HAS_EGPR=1
REXB4=1 REXB=1 RM=0x3  | OUTREG=XED_REG_R27D HAS_EGPR=1
REXB4=1 REXB=1 RM=0x4  | OUTREG=XED_REG_R28D HAS_EGPR=1
REXB4=1 REXB=1 RM=0x5  | OUTREG=XED_REG_R29D HAS_EGPR=1
REXB4=1 REXB=1 RM=0x6  | OUTREG=XED_REG_R30D HAS_EGPR=1
REXB4=1 REXB=1 RM=0x7  | OUTREG=XED_REG_R31D HAS_EGPR=1


xed_reg_enum_t GPR32_SB()::
REXB4=0 REXB=0 SRM=0x0  | OUTREG=XED_REG_EAX
REXB4=0 REXB=0 SRM=0x1  | OUTREG=XED_REG_ECX
REXB4=0 REXB=0 SRM=0x2  | OUTREG=XED_REG_EDX
REXB4=0 REXB=0 SRM=0x3  | OUTREG=XED_REG_EBX
REXB4=0 REXB=0 SRM=0x4  | OUTREG=XED_REG_ESP
REXB4=0 REXB=0 SRM=0x5  | OUTREG=XED_REG_EBP
REXB4=0 REXB=0 SRM=0x6  | OUTREG=XED_REG_ESI
REXB4=0 REXB=0 SRM=0x7  | OUTREG=XED_REG_EDI
REXB4=0 REXB=1 SRM=0x0  | OUTREG=XED_REG_R8D
REXB4=0 REXB=1 SRM=0x1  | OUTREG=XED_REG_R9D
REXB4=0 REXB=1 SRM=0x2  | OUTREG=XED_REG_R10D
REXB4=0 REXB=1 SRM=0x3  | OUTREG=XED_REG_R11D
REXB4=0 REXB=1 SRM=0x4  | OUTREG=XED_REG_R12D
REXB4=0 REXB=1 SRM=0x5  | OUTREG=XED_REG_R13D
REXB4=0 REXB=1 SRM=0x6  | OUTREG=XED_REG_R14D
REXB4=0 REXB=1 SRM=0x7  | OUTREG=XED_REG_R15D
#EGPRs
REXB4=1 REXB=0 SRM=0x0  | OUTREG=XED_REG_R16D HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x1  | OUTREG=XED_REG_R17D HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x2  | OUTREG=XED_REG_R18D HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x3  | OUTREG=XED_REG_R19D HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x4  | OUTREG=XED_REG_R20D HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x5  | OUTREG=XED_REG_R21D HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x6  | OUTREG=XED_REG_R22D HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x7  | OUTREG=XED_REG_R23D HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x0  | OUTREG=XED_REG_R24D HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x1  | OUTREG=XED_REG_R25D HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x2  | OUTREG=XED_REG_R26D HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x3  | OUTREG=XED_REG_R27D HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x4  | OUTREG=XED_REG_R28D HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x5  | OUTREG=XED_REG_R29D HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x6  | OUTREG=XED_REG_R30D HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x7  | OUTREG=XED_REG_R31D HAS_EGPR=1


#############################


xed_reg_enum_t GPR16_R()::
REXR4=0 REXR=0 REG=0x0  | OUTREG=XED_REG_AX
REXR4=0 REXR=0 REG=0x1  | OUTREG=XED_REG_CX
REXR4=0 REXR=0 REG=0x2  | OUTREG=XED_REG_DX
REXR4=0 REXR=0 REG=0x3  | OUTREG=XED_REG_BX
REXR4=0 REXR=0 REG=0x4  | OUTREG=XED_REG_SP
REXR4=0 REXR=0 REG=0x5  | OUTREG=XED_REG_BP
REXR4=0 REXR=0 REG=0x6  | OUTREG=XED_REG_SI
REXR4=0 REXR=0 REG=0x7  | OUTREG=XED_REG_DI
REXR4=0 REXR=1 REG=0x0  | OUTREG=XED_REG_R8W
REXR4=0 REXR=1 REG=0x1  | OUTREG=XED_REG_R9W
REXR4=0 REXR=1 REG=0x2  | OUTREG=XED_REG_R10W
REXR4=0 REXR=1 REG=0x3  | OUTREG=XED_REG_R11W
REXR4=0 REXR=1 REG=0x4  | OUTREG=XED_REG_R12W
REXR4=0 REXR=1 REG=0x5  | OUTREG=XED_REG_R13W
REXR4=0 REXR=1 REG=0x6  | OUTREG=XED_REG_R14W
REXR4=0 REXR=1 REG=0x7  | OUTREG=XED_REG_R15W
#EGPRs
REXR4=1 REXR=0 REG=0x0  | OUTREG=XED_REG_R16W HAS_EGPR=1
REXR4=1 REXR=0 REG=0x1  | OUTREG=XED_REG_R17W HAS_EGPR=1
REXR4=1 REXR=0 REG=0x2  | OUTREG=XED_REG_R18W HAS_EGPR=1
REXR4=1 REXR=0 REG=0x3  | OUTREG=XED_REG_R19W HAS_EGPR=1
REXR4=1 REXR=0 REG=0x4  | OUTREG=XED_REG_R20W HAS_EGPR=1
REXR4=1 REXR=0 REG=0x5  | OUTREG=XED_REG_R21W HAS_EGPR=1
REXR4=1 REXR=0 REG=0x6  | OUTREG=XED_REG_R22W HAS_EGPR=1
REXR4=1 REXR=0 REG=0x7  | OUTREG=XED_REG_R23W HAS_EGPR=1
REXR4=1 REXR=1 REG=0x0  | OUTREG=XED_REG_R24W HAS_EGPR=1
REXR4=1 REXR=1 REG=0x1  | OUTREG=XED_REG_R25W HAS_EGPR=1
REXR4=1 REXR=1 REG=0x2  | OUTREG=XED_REG_R26W HAS_EGPR=1
REXR4=1 REXR=1 REG=0x3  | OUTREG=XED_REG_R27W HAS_EGPR=1
REXR4=1 REXR=1 REG=0x4  | OUTREG=XED_REG_R28W HAS_EGPR=1
REXR4=1 REXR=1 REG=0x5  | OUTREG=XED_REG_R29W HAS_EGPR=1
REXR4=1 REXR=1 REG=0x6  | OUTREG=XED_REG_R30W HAS_EGPR=1
REXR4=1 REXR=1 REG=0x7  | OUTREG=XED_REG_R31W HAS_EGPR=1


xed_reg_enum_t GPR16_B()::
REXB4=0 REXB=0 RM=0x0  | OUTREG=XED_REG_AX
REXB4=0 REXB=0 RM=0x1  | OUTREG=XED_REG_CX
REXB4=0 REXB=0 RM=0x2  | OUTREG=XED_REG_DX
REXB4=0 REXB=0 RM=0x3  | OUTREG=XED_REG_BX
REXB4=0 REXB=0 RM=0x4  | OUTREG=XED_REG_SP
REXB4=0 REXB=0 RM=0x5  | OUTREG=XED_REG_BP
REXB4=0 REXB=0 RM=0x6  | OUTREG=XED_REG_SI
REXB4=0 REXB=0 RM=0x7  | OUTREG=XED_REG_DI
REXB4=0 REXB=1 RM=0x0  | OUTREG=XED_REG_R8W
REXB4=0 REXB=1 RM=0x1  | OUTREG=XED_REG_R9W
REXB4=0 REXB=1 RM=0x2  | OUTREG=XED_REG_R10W
REXB4=0 REXB=1 RM=0x3  | OUTREG=XED_REG_R11W
REXB4=0 REXB=1 RM=0x4  | OUTREG=XED_REG_R12W
REXB4=0 REXB=1 RM=0x5  | OUTREG=XED_REG_R13W
REXB4=0 REXB=1 RM=0x6  | OUTREG=XED_REG_R14W
REXB4=0 REXB=1 RM=0x7  | OUTREG=XED_REG_R15W
#EGPRs
REXB4=1 REXB=0 RM=0x0  | OUTREG=XED_REG_R16W HAS_EGPR=1
REXB4=1 REXB=0 RM=0x1  | OUTREG=XED_REG_R17W HAS_EGPR=1
REXB4=1 REXB=0 RM=0x2  | OUTREG=XED_REG_R18W HAS_EGPR=1
REXB4=1 REXB=0 RM=0x3  | OUTREG=XED_REG_R19W HAS_EGPR=1
REXB4=1 REXB=0 RM=0x4  | OUTREG=XED_REG_R20W HAS_EGPR=1
REXB4=1 REXB=0 RM=0x5  | OUTREG=XED_REG_R21W HAS_EGPR=1
REXB4=1 REXB=0 RM=0x6  | OUTREG=XED_REG_R22W HAS_EGPR=1
REXB4=1 REXB=0 RM=0x7  | OUTREG=XED_REG_R23W HAS_EGPR=1
REXB4=1 REXB=1 RM=0x0  | OUTREG=XED_REG_R24W HAS_EGPR=1
REXB4=1 REXB=1 RM=0x1  | OUTREG=XED_REG_R25W HAS_EGPR=1
REXB4=1 REXB=1 RM=0x2  | OUTREG=XED_REG_R26W HAS_EGPR=1
REXB4=1 REXB=1 RM=0x3  | OUTREG=XED_REG_R27W HAS_EGPR=1
REXB4=1 REXB=1 RM=0x4  | OUTREG=XED_REG_R28W HAS_EGPR=1
REXB4=1 REXB=1 RM=0x5  | OUTREG=XED_REG_R29W HAS_EGPR=1
REXB4=1 REXB=1 RM=0x6  | OUTREG=XED_REG_R30W HAS_EGPR=1
REXB4=1 REXB=1 RM=0x7  | OUTREG=XED_REG_R31W HAS_EGPR=1

xed_reg_enum_t GPR16_SB()::
REXB4=0 REXB=0 SRM=0x0  | OUTREG=XED_REG_AX
REXB4=0 REXB=0 SRM=0x1  | OUTREG=XED_REG_CX
REXB4=0 REXB=0 SRM=0x2  | OUTREG=XED_REG_DX
REXB4=0 REXB=0 SRM=0x3  | OUTREG=XED_REG_BX
REXB4=0 REXB=0 SRM=0x4  | OUTREG=XED_REG_SP
REXB4=0 REXB=0 SRM=0x5  | OUTREG=XED_REG_BP
REXB4=0 REXB=0 SRM=0x6  | OUTREG=XED_REG_SI
REXB4=0 REXB=0 SRM=0x7  | OUTREG=XED_REG_DI
REXB4=0 REXB=1 SRM=0x0  | OUTREG=XED_REG_R8W
REXB4=0 REXB=1 SRM=0x1  | OUTREG=XED_REG_R9W
REXB4=0 REXB=1 SRM=0x2  | OUTREG=XED_REG_R10W
REXB4=0 REXB=1 SRM=0x3  | OUTREG=XED_REG_R11W
REXB4=0 REXB=1 SRM=0x4  | OUTREG=XED_REG_R12W
REXB4=0 REXB=1 SRM=0x5  | OUTREG=XED_REG_R13W
REXB4=0 REXB=1 SRM=0x6  | OUTREG=XED_REG_R14W
REXB4=0 REXB=1 SRM=0x7  | OUTREG=XED_REG_R15W
#EGPRs
REXB4=1 REXB=0 SRM=0x0  | OUTREG=XED_REG_R16W HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x1  | OUTREG=XED_REG_R17W HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x2  | OUTREG=XED_REG_R18W HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x3  | OUTREG=XED_REG_R19W HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x4  | OUTREG=XED_REG_R20W HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x5  | OUTREG=XED_REG_R21W HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x6  | OUTREG=XED_REG_R22W HAS_EGPR=1
REXB4=1 REXB=0 SRM=0x7  | OUTREG=XED_REG_R23W HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x0  | OUTREG=XED_REG_R24W HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x1  | OUTREG=XED_REG_R25W HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x2  | OUTREG=XED_REG_R26W HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x3  | OUTREG=XED_REG_R27W HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x4  | OUTREG=XED_REG_R28W HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x5  | OUTREG=XED_REG_R29W HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x6  | OUTREG=XED_REG_R30W HAS_EGPR=1
REXB4=1 REXB=1 SRM=0x7  | OUTREG=XED_REG_R31W HAS_EGPR=1


#############################

# GPR8_R and GPR8_B are handled in separate files -- grep for them.

###########################a

xed_reg_enum_t CR_R()::
REXR4=0 REXR=0 REG=0x0  | OUTREG=XED_REG_CR0
REXR4=0 REXR=0 REG=0x1  | OUTREG=XED_REG_ERROR  enc
REXR4=0 REXR=0 REG=0x2  | OUTREG=XED_REG_CR2
REXR4=0 REXR=0 REG=0x3  | OUTREG=XED_REG_CR3
REXR4=0 REXR=0 REG=0x4  | OUTREG=XED_REG_CR4
REXR4=0 REXR=0 REG=0x5  | OUTREG=XED_REG_ERROR
REXR4=0 REXR=0 REG=0x6  | OUTREG=XED_REG_ERROR
REXR4=0 REXR=0 REG=0x7  | OUTREG=XED_REG_ERROR
REXR4=0 REXR=1 REG=0x0  | OUTREG=XED_REG_CR8
REXR4=0 REXR=1 REG=0x1  | OUTREG=XED_REG_ERROR
REXR4=0 REXR=1 REG=0x2  | OUTREG=XED_REG_ERROR
REXR4=0 REXR=1 REG=0x3  | OUTREG=XED_REG_ERROR
REXR4=0 REXR=1 REG=0x4  | OUTREG=XED_REG_ERROR
REXR4=0 REXR=1 REG=0x5  | OUTREG=XED_REG_ERROR
REXR4=0 REXR=1 REG=0x6  | OUTREG=XED_REG_ERROR
REXR4=0 REXR=1 REG=0x7  | OUTREG=XED_REG_ERROR
REXR4=1                 | OUTREG=XED_REG_ERROR

# FIXME: not used
xed_reg_enum_t CR_B()::
REXR4=0 REXB=0 RM=0x0  | OUTREG=XED_REG_CR0
REXR4=0 REXB=0 RM=0x1  | OUTREG=XED_REG_ERROR   enc
REXR4=0 REXB=0 RM=0x2  | OUTREG=XED_REG_CR2
REXR4=0 REXB=0 RM=0x3  | OUTREG=XED_REG_CR3
REXR4=0 REXB=0 RM=0x4  | OUTREG=XED_REG_CR4
REXR4=0 REXB=0 RM=0x5  | OUTREG=XED_REG_ERROR
REXR4=0 REXB=0 RM=0x6  | OUTREG=XED_REG_ERROR
REXR4=0 REXB=0 RM=0x7  | OUTREG=XED_REG_ERROR
REXR4=0 REXB=1 RM=0x0  | OUTREG=XED_REG_CR8
REXR4=0 REXB=1 RM=0x1  | OUTREG=XED_REG_ERROR
REXR4=0 REXB=1 RM=0x2  | OUTREG=XED_REG_ERROR
REXR4=0 REXB=1 RM=0x3  | OUTREG=XED_REG_ERROR
REXR4=0 REXB=1 RM=0x4  | OUTREG=XED_REG_ERROR
REXR4=0 REXB=1 RM=0x5  | OUTREG=XED_REG_ERROR
REXR4=0 REXB=1 RM=0x6  | OUTREG=XED_REG_ERROR
REXR4=0 REXB=1 RM=0x7  | OUTREG=XED_REG_ERROR
REXR4=1                | OUTREG=XED_REG_ERROR

########################

xed_reg_enum_t DR_R()::
REXR4=0 REXR=0 REG=0x0  | OUTREG=XED_REG_DR0
REXR4=0 REXR=0 REG=0x1  | OUTREG=XED_REG_DR1
REXR4=0 REXR=0 REG=0x2  | OUTREG=XED_REG_DR2
REXR4=0 REXR=0 REG=0x3  | OUTREG=XED_REG_DR3
REXR4=0 REXR=0 REG=0x4  | OUTREG=XED_REG_DR4
REXR4=0 REXR=0 REG=0x5  | OUTREG=XED_REG_DR5
REXR4=0 REXR=0 REG=0x6  | OUTREG=XED_REG_DR6
REXR4=0 REXR=0 REG=0x7  | OUTREG=XED_REG_DR7
REXR4=0 REXR=1 REG=0x0  | OUTREG=XED_REG_ERROR enc
REXR4=0 REXR=1 REG=0x1  | OUTREG=XED_REG_ERROR
REXR4=0 REXR=1 REG=0x2  | OUTREG=XED_REG_ERROR
REXR4=0 REXR=1 REG=0x3  | OUTREG=XED_REG_ERROR
REXR4=0 REXR=1 REG=0x4  | OUTREG=XED_REG_ERROR
REXR4=0 REXR=1 REG=0x5  | OUTREG=XED_REG_ERROR
REXR4=0 REXR=1 REG=0x6  | OUTREG=XED_REG_ERROR
REXR4=0 REXR=1 REG=0x7  | OUTREG=XED_REG_ERROR
REXR4=1                 | OUTREG=XED_REG_ERROR

