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#address-cells#size-cellsmodelcompatiblestdout-pathethernet0can0can1gpio0gpio1gpio2gpio3gpio4gpio5gpio6i2c0i2c1i2c2ipu0mmc0mmc1mmc2mmc3serial0serial1serial2serial3serial4spi0spi1spi2spi3usbphy0usbphy1i2c3#clock-cellsclock-frequencyinterrupt-parentinterruptsfsl,tempmonfsl,tempmon-dataclocks#thermal-sensor-cellsgprstatusclock-namesregremote-endpointphandle#phy-cellsrangesinterrupt-names#dma-cellsdma-channelsreg-namesdmasdma-namespinctrl-namespinctrl-0nand-on-flash-bbtpower-domains#cooling-cells#interrupt-cellsinterrupt-controllercache-unifiedcache-levelarm,tag-latencyarm,data-latencyarm,shared-overridedevice_typebus-rangenum-lanesnum-viewportinterrupt-map-maskinterrupt-mapreset-gpiocs-gpiosspi-max-frequency#sound-dai-cellsfsl,fifo-depthfsl,asrc-ratefsl,asrc-widthresetsiram#pwm-cellsfsl,stop-modegpio-controller#gpio-cellsgpio-rangesregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onanatop-reg-offsetanatop-vol-bit-shiftanatop-vol-bit-widthanatop-min-bit-valanatop-min-voltageanatop-max-voltageanatop-enable-bitanatop-delay-reg-offsetanatop-delay-bit-shiftanatop-delay-bit-widthvin-supplyregulator-enable-ramp-delayfsl,anatopregmapvaluelinux,keycodewakeup-source#reset-cells#power-domain-cellspower-supply#mux-control-cellsmux-reg-masksmux-controlsfsl,pinsfsl,sdma-ram-script-namefsl,usbphyfsl,usbmiscahb-burst-configtx-burst-size-dwordrx-burst-size-dwordvbus-supplydisable-over-currentdr_modephy_type#index-cellsinterrupts-extendedphy-handlephy-modephy-reset-durationphy-reset-gpiosphy-supplytxc-skew-psrxc-skew-psbus-widthcd-gpioswp-gpiosai3x-micbias-vgAVDD-supplyIOVDD-supplyDRVDD-supplyDVDD-supplyfsl,weim-cs-gprfsl,audmux-portfsl,port-confignext-level-cacheoperating-pointsfsl,soc-operating-pointsclock-latencyarm-supplypu-supplysoc-supplyportsenable-active-highlabelclock-output-namessimple-audio-card,namesimple-audio-card,formatsimple-audio-card,bitclock-mastersimple-audio-card,frame-mastersimple-audio-card,widgetssimple-audio-card,routingsound-dai