~8w(( Vv Fairphone 2!fairphone,fp2qcom,msm8974,reserved-memory=mpss@8000000DHO/mba@d100000D HO.wcnss@d200000D HO0adsp@dc00000D HOvenus@f500000DPPHsmem@fa00000D HOtz@fc00000DHrfsa@fd60000DHrmtfs@fd80000!qcom,rmtfs-memDHWcpus f cpu@0 !qcom,kraitqqcom,kpss-acc-v2cpuDOOcpu@1 !qcom,kraitqqcom,kpss-acc-v2cpuDOQcpu@2 !qcom,kraitqqcom,kpss-acc-v2cpuD OScpu@3 !qcom,kraitqqcom,kpss-acc-v2cpuD  OUl2-cache!cache Oidle-statesspc#!qcom,idle-state-spcarm,idle-stateOmemorymemoryDthermal-zonescpu-thermal0 tripstrip00$<passivetrip10< criticalcpu-thermal1 tripstrip00$<passivetrip10< criticalcpu-thermal2 tripstrip00$<passivetrip10< criticalcpu-thermal3 tripstrip00$<passivetrip10< criticalq6-dsp-thermal tripstrip-point00_<hotmodemtx-thermal tripstrip-point00_<hotvideo-thermal tripstrip-point00s<hotwlan-thermal tripstrip-point00(<hotgpu-thermal-top tripstrip-point00_<hotgpu-thermal-bottom tripstrip-point00_<hotcpu-pmu!qcom,krait-pmu fclocksxo_board !fixed-clockGT$Osleep_clk !fixed-clockGTtimer!arm,armv7-timer0fT$adsp-pil!qcom,msm8974-adsp-pil@d#xwdogfatalreadyhandoverstop-ackxostopsmd-edge f lpasssmem !qcom,smemsmp2p-adsp !qcom,smp2p, f  )master-kernel9master-kernelIOslave-kernel 9slave-kernel`uOsmp2p-modem !qcom,smp2p, f )master-kernel9master-kernelIO-slave-kernel 9slave-kernel`uO)smp2p-wcnss !qcom,smp2p, f )master-kernel9master-kernelIO2slave-kernel 9slave-kernel`uO1smsm !qcom,smsm     apps@0DIO8modem@1D f`uadsp@2D f`uwcnss@7D f`ufirmwarescm !qcom,scmcorebusifacesoc= !simple-businterrupt-controller@f9000000!qcom,msm-qgic2`uD Osyscon@f9011000!sysconDOqfprom@fc4bc000 !qcom,qfpromDKcalib@d0DObackup@440D@Othermal-sensor@fc4a9000!qcom,msm8974-tsensDJJcalibcalib_backup  fxuplowO timer@f9020000=!arm,armv7-timer-memDT$frame@f9021000fD frame@f9023000 f D0 disabledframe@f9024000 f D@ disabledframe@f9025000 f DP disabledframe@f9026000 f D` disabledframe@f9027000 f Dp disabledframe@f9028000 fD disabledpower-controller@f9089000%!qcom,msm8974-saw2-v2.1-cpuqcom,saw2DOpower-controller@f9099000%!qcom,msm8974-saw2-v2.1-cpuqcom,saw2D Opower-controller@f90a9000%!qcom,msm8974-saw2-v2.1-cpuqcom,saw2D O power-controller@f90b9000%!qcom,msm8974-saw2-v2.1-cpuqcom,saw2D O power-controller@f9012000 !qcom,saw2D O clock-controller@f9088000!qcom,kpss-acc-v2DOclock-controller@f9098000!qcom,kpss-acc-v2D Oclock-controller@f90a8000!qcom,kpss-acc-v2D Oclock-controller@f90b8000!qcom,kpss-acc-v2D O restart@fc4ab000 !qcom,psholdDJclock-controller@fc400000!qcom,gcc-msm8974GD@@Osyscon@fd4a0000!sysconDJO"syscon@fd484000!sysconDH@ Oclock-controller@fd8c0000!qcom,mmcc-msm8974GD`OWtcsr-mutex!qcom,tcsr-mutex '.Omemory@fc428000!qcom,rpm-msg-ramDB@Oserial@f991d000%!qcom,msm-uartdm-v1.4qcom,msm-uartdmD fkeW coreiface disabledserial@f991e000%!qcom,msm-uartdm-v1.4qcom,msm-uartdmD flgW coreifaceokserial@f9960000%!qcom,msm-uartdm-v1.4qcom,msm-uartdmD ftq coreiface disabledsdhci@f9824900%!qcom,msm8974-sdhciqcom,sdhci-msm-v4DI@s4-LK@ELK@]O>5vs1]y O;5vs2]y dma-controller@f9944000!qcom,bam-v1.4.0D@ fqbam_clk O:etr@fc322000 !arm,coresight-tmcarm,primecellD2 44 apb_pclkatclkin-portsportendpoint?OAtpiu@fc318000!!arm,coresight-tpiuarm,primecellD144 apb_pclkatclkin-portsportendpoint@OBreplicator@fc31c000/!arm,coresight-dynamic-replicatorarm,primecellD144 apb_pclkatclkout-portsport@0DendpointAO?port@1DendpointBO@in-portsportendpointCODetf@fc307000 !arm,coresight-tmcarm,primecellD0p44 apb_pclkatclkout-portsportendpointDOCin-portsportendpointEOGfunnel@fc31b000+!arm,coresight-dynamic-funnelarm,primecellD144 apb_pclkatclkin-portsport@1DendpointFOIout-portsportendpointGOEfunnel@fc31a000+!arm,coresight-dynamic-funnelarm,primecellD144 apb_pclkatclkin-portsport@5DendpointHONout-portsportendpointIOFfunnel@fc345000+!arm,coresight-dynamic-funnelarm,primecellD4P44 apb_pclkatclkin-portsport@0DendpointJOPport@1DendpointKORport@2DendpointLOTport@3DendpointMOVout-portsportendpointNOHetm@fc33c000"!arm,coresight-etm4xarm,primecellD344 apb_pclkatclk'Oout-portsportendpointPOJetm@fc33d000"!arm,coresight-etm4xarm,primecellD344 apb_pclkatclk'Qout-portsportendpointROKetm@fc33e000"!arm,coresight-etm4xarm,primecellD344 apb_pclkatclk'Sout-portsportendpointTOLetm@fc33f000"!arm,coresight-etm4xarm,primecellD344 apb_pclkatclk'Uout-portsportendpointVOMocmem@fdd00000!qcom,msm8974-ocmemD  9V Kc #address-cells#size-cellsmodelcompatibleinterrupt-parentrangesregno-mapphandleqcom,client-idinterruptsenable-methoddevice_typenext-level-cacheqcom,accqcom,sawcpu-idle-statescache-levelentry-latency-usexit-latency-usmin-residency-uspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresis#clock-cellsclock-frequencyinterrupts-extendedinterrupt-namescx-supplyclocksclock-namesmemory-regionqcom,smem-statesqcom,smem-state-namesqcom,ipcqcom,smd-edgelabelqcom,rpm-msg-ramhwlocksqcom,smemqcom,local-pidqcom,remote-pidqcom,entry-name#qcom,smem-state-cellsinterrupt-controller#interrupt-cellsqcom,ipc-1qcom,ipc-2qcom,ipc-3nvmem-cellsnvmem-cell-names#qcom,sensors#thermal-sensor-cellsframe-numberstatusregulator#reset-cells#power-domain-cellssyscon#hwlock-cellsreg-namesvmmc-supplyvqmmc-supplybus-widthnon-removablepinctrl-namespinctrl-0assigned-clocksassigned-clock-ratesresetsreset-namesphy_typedr_modeahb-burst-configphy-namesphysphy-selectextconvbus-supplyhnp-disablesrp-disableadp-disable#phy-cellsv1p8-supplyv3p3-supplyqcom,init-seqmss-supplymx-supplypll-supplyqcom,halt-regsvddpx-supplyvddmx-supplyvddcx-supplyvddxo-supplyvddrfa-supplyvddpa-supplyvdddig-supplyqcom,smd-channelsqcom,mmiogpio-controllergpio-ranges#gpio-cellspinsdrive-strengthbias-disablebias-pull-upfunctionbias-pull-downdmasdma-namesqcom,eeqcom,channeldebounceusb-otg-in-supplypower-sourceio-channelsio-channel-names#io-channel-cellsqcom,external-resistor-micro-ohmsvin_5vs-supplyregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-pull-downregulator-over-current-protectionqcom,ocp-max-retriesqcom,ocp-retry-delayqcom,vs-soft-start-strengthregulator-initial-mode#dma-cellsremote-endpointcpu#interconnect-cellspower-domainsinterconnectsinterconnect-namesassigned-clock-parentsqcom,dsi-phy-indexoffsetmode-normalmode-bootloadermode-recoveryvdd_l1_l3-supplyvdd_l2_lvs1_2_3-supplyvdd_l4_l11-supplyvdd_l5_l7-supplyvdd_l6_l12_l14_l15-supplyvdd_l9_l10_l17_l22-supplyvdd_l13_l20_l23_l24-supplyvdd_l21-supplyregulator-always-onregulator-boot-onregulator-system-loadregulator-allow-set-loadregulator-namegpioenable-active-highserial0stdout-pathinput-namegpioslinux,codewakeup-sourcedebounce-intervalenable-gpiosvcc-supply