Ð þí ˆ8¬(Üt%xlnx,zynq-zc770-xm010xlnx,zynq-7000&Xilinx ZC770 XM010 boardcpuscpu@0arm,cortex-a9,cpu8<CèQ] ,+B@B@cpu@1arm,cortex-a9,cpu8<fpga-full fpga-regionnwpmu@f8891000arm,cortex-a9-pmu~‰8ø‰ø‰0fixedregulatorregulator-fixedšVCCPINT©B@ÁB@Ùëÿamba simple-bus‰wadc@f8007100xlnx,zynq-xadc-1.00.a8øq  ~‰< can@e0008000xlnx,zynq-can-1.0okay<$ can_clkpclk8à€ ~‰@(@can@e0009000xlnx,zynq-can-1.0 disabled<% can_clkpclk8à ~3‰@(@gpio@e000a000xlnx,zynq-gpio-1.06<*BRg‰ ~8à i2c@e0004000cdns,i2c-r1p10okay<&‰ ~8à@x€eeprom@52 atmel,24c028Ri2c@e0005000cdns,i2c-r1p10 disabled<'‰ ~08àPinterrupt-controller@f8f01000arm,cortex-a9-gicgR8øðøðÿcache-controller@f8f02000arm,pl310-cache8øð  ~ ˆ ™©·memory-controller@f8006000xlnx,zynq-ddrc-a058ø`serial@e0000000xlnx,xuartpscdns,uart-r1p8 disabled<(uart_clkpclk8à ~serial@e0001000xlnx,xuartpscdns,uart-r1p8okay<)uart_clkpclk8à ~2spi@e0006000xlnx,zynq-spi-r1p68à` disabled‰ ~<" ref_clkpclkspi@e0007000xlnx,zynq-spi-r1p68àpokay‰ ~1<# ref_clkpclkÃÊflash@1sst25wf080jedec,spi-nor8ØB@partitionsfixed-partitionspartition@0êdata8ethernet@e000b000cdns,zynq-gemcdns,gem8à°okay ~< pclkhclktx_clk ðrgmii-idùethernet-phy@78 ,ethernet-phyÿethernet@e000c000cdns,zynq-gemcdns,gem8àÀ disabled ~-<pclkhclktx_clkmmc@e0100000arasan,sdhci-8.9aokayclk_xinclk_ahb< ‰ ~8àmmc@e0101000arasan,sdhci-8.9a disabledclk_xinclk_ahb<!‰ ~/8àslcr@f8000000!xlnx,zynq-slcrsysconsimple-mfd8øwÿclkc@100xlnx,ps7-clkcjarmpllddrplliopllcpu_6or4xcpu_3or2xcpu_2xcpu_1xddr2xddr3xdcilqspismcpcapgem0gem1fclk0fclk1fclk2fclk3can0can1sdio0sdio1uart0uart1spi0spi1dmausb0_aperusb1_apergem0_apergem1_apersdio0_apersdio1_aperspi0_aperspi1_apercan0_apercan1_aperi2c0_aperi2c1_aperuart0_aperuart1_apergpio_aperlqspi_apersmc_aperswdtdbg_trcdbg_apb8ÿrstc@200xlnx,zynq-reset8H0=pinctrl@700xlnx,pinctrl-zynq8=dmac@f8003000arm,pl330arm,primecell8ø0‰.Dabortdma0dma1dma2dma3dma4dma5dma6dma7l~ ()*+T_m< apb_pclkdevcfg@f8007000xlnx,zynq-devcfg-1.08øp‰ ~< ref_clk=ÿtimer@f8f00200arm,cortex-a9-global-timer8øð  ~ ‰<timer@f8001000‰$~    cdns,ttc<8øtimer@f8002000‰$~%&' cdns,ttc<8ø timer@f8f00600‰ ~ arm,cortex-a9-twd-timer8øð <usb@e0002000"xlnx,zynq-usb-2.20achipidea,usb2okay<‰ ~8à {ulpi„hostŒusb@e0003000"xlnx,zynq-usb-2.20achipidea,usb2 disabled<‰ ~,8à0{ulpiwatchdog@f8005000<-cdns,wdt-r1p2‰ ~ 8øP” aliases /amba/ethernet@e000b000ª/amba/i2c@e0004000¯/amba/serial@e0001000·/amba/spi@e0007000chosen¼Åserial0:115200n8memory@0,memory8@phy0usb-nop-xceivÑÿ #address-cells#size-cellscompatiblemodeldevice_typeregclocksclock-latencycpu0-supplyoperating-pointsfpga-mgrrangesinterruptsinterrupt-parentregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onregulator-always-onphandlestatusclock-namestx-fifo-depthrx-fifo-depth#gpio-cellsgpio-controllerinterrupt-controller#interrupt-cellsclock-frequencyarm,data-latencyarm,tag-latencycache-unifiedcache-levelnum-csis-decoded-csspi-max-frequencylabelphy-modephy-handle#clock-cellsfclk-enableclock-output-names#reset-cellssysconinterrupt-names#dma-cells#dma-channels#dma-requestsphy_typedr_modeusb-phytimeout-secethernet0i2c0serial0spi1bootargsstdout-path#phy-cells